Table 41 lists major changes " />
參數(shù)資料
型號(hào)： PC56F8006VWL
廠商： Freescale Semiconductor
文件頁(yè)數(shù)： 89/106頁(yè)
文件大小： 0K
描述： DSP 16BIT 28-SOIC
標(biāo)準(zhǔn)包裝： 26
系列： 56F8xxx
核心處理器： 56800
芯體尺寸： 16-位
速度： 32MHz
連通性： I²C，LIN，SCI，SPI
外圍設(shè)備： LVD，POR，PWM，WDT
輸入/輸出數(shù)： 23
程序存儲(chǔ)器容量： 16KB（8K x 16）
程序存儲(chǔ)器類型： 閃存
RAM 容量： 1K x 16
電壓 - 電源 (Vcc/Vdd)： 1.8 V ~ 3.6 V
數(shù)據(jù)轉(zhuǎn)換器： A/D 15x12b
振蕩器型： 內(nèi)部
工作溫度： -40°C ~ 105°C
封裝/外殼： 28-SOIC（0.295"，7.50mm 寬）
包裝： 管件
Revision History
MC56F8006/MC56F8002 Digital Signal Controller, Rev. 4
Freescale Semiconductor
83
11
Revision History
Table 41 lists major changes between versions of the MC56F8006 document.
Appendix A
Interrupt Vector Table
Table 43 provides the 56F8006/56F8002’s reset and interrupt priority structure, including on-chip peripherals. The table is
organized with higher-priority vectors at the top and lower-priority interrupts lower in the table. As indicated, the priority of an
interrupt can be assigned to different levels, allowing some control over interrupt priorities. All level 3 interrupts are serviced
before level 2 and so on. For a selected priority level, the lowest vector number has the highest priority.
The location of the vector table is determined by the vector base address (VBA). Please see the MC56F8006 Peripheral
Reference Manual for detail.
By default, the chip reset address and COP reset address correspond to vector 0 and 1 of the interrupt vector table. In these
instances, the first two locations in the vector table must contain branch or JMP instructions. All other entries must contain JSR
instructions.
Table 41. Changes Between Revisions 2 and 3
Location
Description
Introduction on page 1
Added part marking for devices covered by this document
Updated routing details for ANB24 and ANB25
Removed row about open drain mode (GPIO supports only push-pull mode)
Updated specifications for low-voltage detection threshold (high and low range) and
low-voltage warning threshold
Updated all Supply Current Consumption specifications
Updated ROSC variation over temperature specifications (both ranges)
Removed I2C fast mode specifications and footnote about setup time if the TX FIFO
is empty (fast mode and FIFO not supported)
Appendix B on page 86
Added note explaining ADC and GPIO naming conventions
For I2C_SMB_CSR, clarified that bits 7 and 6 are reserved
Table 42. Changes Between Revisions 3 and 4
Location
Description
Throughout document.
Added information for 32-pin PSDIP device and devices with temperature range
from –40
C to + 125 C.
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