17
PC7457/47 [Preliminary]
5345B–HIREL–02/04
R
θ
JC
is the junction-to-case thermal resistance
R
θ
int
is the adhesive or interface material thermal resistance
R
θ
sa
is the heat sink base-to-ambient thermal resistance
P
d
is the power dissipated by the device
During operation, the die-junction temperatures (T
j
) should be maintained less than the
value specified in Table 3 on page 12. The temperature of air cooling the component
greatly depends on the ambient inlet air temperature and the air temperature rise within
the electronic cabinet. An electronic cabinet inlet-air temperature (T
a
) may range from
30
°
to 40
°
C. The air temperature rise within a cabinet (T
r
) may be in the range of 5
°
to
10
°
C.
The thermal resistance of the thermal interface material (R
θ
int
) is typically about
1.5
°
C/W. For example, assuming a Ta of 30
°
C, a Tr of 5
°
C, a CBGA package R
θ
JC
=
0.1, and a typical power consumption (P
d
) of 18.7W, the following expression for T
j
is
obtained:
Die-junction temperature: T
j
= 30
°
C + 5
°
C + (0.1
°
C/W + 1.5
°
C/W +
θ
sa
)
×
18.7W
For this example, a R
θ
sa
value of 2.1
°
C/W or less is required to maintain the die junction
temperature below the maximum value of Table 3 on page 12.
Though the die junction-to-ambient and the heat sink-to-ambient thermal resistances
are a common figure-of-merit used for comparing the thermal performance of various
microelectronic packaging technologies, one should exercise caution when only using
this metric in determining thermal management because no single parameter can ade-
quately describe three-dimensional heat flow. The final die-junction operating
temperature is not only a function of the component-level thermal resistance, but the
system-level design and its operating conditions. In addition to the component's power
consumption, a number of factors affect the final operating die-junction temperature –
airflow, board population (local heat flux of adjacent components), heat sink efficiency,
heat sink attach, heat sink placement, next-level interconnect technology, system air
temperature rise, altitude, etc.
Due to the complexity and the many variations of system-level boundary conditions for
today's microelectronic equipment, the combined effects of the heat transfer mecha-
nisms (radiation, convection, and conduction) may vary widely. For these reasons, we
recommend using conjugate heat transfer models for the board, as well as system-level
designs.
For system thermal modeling, the PC7447 and PC7457 thermal model is shown in Fig-
ure 4 on page 14. Four volumes will be used to represent this device. Two of the
volumes, solder ball, and air and substrate, are modeled using the package outline size
of the package. The other two, die, and bump and underfill, have the same size as the
die. The silicon die should be modeled 9.64
×
11 × 0.74 mm with the heat source applied
as a uniform source at the bottom of the volume. The bump and underfill layer is mod-
eled as 9.64
×
11
×
0.69 mm (or as a collapsed volume) with orthotropic material
properties: 0.6W/(m × K) in the
x
y-plane and 2W/(m × K) in the direction of the z-axis.
The substrate volume is 25
×
25
×
1.2 mm (PC7447) or 29
×
29
×
1.2 mm (PC7457), and
this volume has 18W/(m × K) isotropic conductivity. The solder ball and air layer is mod-
eled with the same horizontal dimensions as the substrate and is 0.9 mm thick. It can
also be modeled as a collapsed volume using orthotropic material properties:
0.034W/(m × K) in the xy-plane direction and 3.8W/(m × K) in the direction of the z-axis.