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| 型號： | PC7447VG1200N |
| 廠商： | Atmel Corp. |
| 英文描述： | PowerPC 7457 RISC Microprocessor |
| 中文描述： | 7457的PowerPC RISC微處理器 |
| 文件頁數(shù)： | 22/66頁 |
| 文件大?。?/td> | 522K |
| 代理商： | PC7447VG1200N |
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22
PC7457/47 [Preliminary]
5345B–HIREL–02/04
Processor Bus AC
Specifications
Table 9 provides the processor bus AC timing specifications for the PC7457 as defined
in Figure 17 on page 34 and Figure 9 on page 23. Timing specifications for the L3 bus
are provided in section “L3 Clock AC Specifications” on page 24.
Notes:
1. All input specifications are measured from the midpoint of the signal in question to the midpoint of the rising edge of the input
SYSCLK. All output specifications are measured from the midpoint of the rising edge of SYSCLK to the midpoint of the sig-
nal in question. All output timings assume a purely resistive 50
load (see Figure 17 on page 34). Input and output timings
are measured at the pin; time-of-flight delays must be added for trace lengths, vias, and connectors in the system.
Table 9.
Processor Bus AC Timing Specifications
(1)
(at Recommended Operating Conditions, see Table 3 on page 12.)
Symbol
(2)
Parameter
All Speed Grades
Unit
V
DD
= 1.1V
Min
V
DD
= 1.3V
Max
t
AVKH
t
DVKH
t
IVKH
t
MVKH
(8)
Input setup times:
A[0:35], AP[0:4]
D[0:63], DP[0:7]
AACK, ARTRY, BG, CKSTP_IN, DBG, DTI[0:3], GBL,
TT[0:3], QACK, TA, TBEN, TEA, TS,
EXT_QUAL, PMON_IN, SHD[0:1],
BMODE[0:1], BMODE[0:1], BVSEL, L3VSEL
2.0
2.0
2.0
2
1.8
1.8
1.8
1.8
–
–
–
–
ns
t
AXKH
t
DXKH
t
IXKH
t
MXKH
(8)
Input hold times:
A[0:35], AP[0:4]
D[0:63], DP[0:7]
AACK, ARTRY, BG, CKSTP_IN, DBG, DTI[0:3], GBL,
TT[0:3], QACK, TA, TBEN, TEA, TS, EXT_QUAL,
PMON_IN, SHD[0:1]
BMODE[0:1], BMODE[0:1], BVSEL, L3VSEL
0
0
0
0
0
0
0
0
–
–
–
–
ns
t
KHAV
t
KHDV
t
KHOV
Output valid times:
A[0:35], AP[0:4]
D[0:63], DP[0:7]
AACK, ARTRY, BR, CI, CKSTP_IN, DRDY, DTI[0:3],
GBL, HIT, PMON_OUT, QREQ, TBST, TSIZ[0:2], TT[0:3],
TS, SHD[0:1], WT
–
–
–
–
–
–
2
2
2
ns
t
KHAX
t
KHDX
t
KHOX
Output hold times:
A[0:35], AP[0:4]
D[0:63], DP[0:7]
AACK, ARTRY, BR, CI, CKSTP_IN, DRDY, DTI[0:3],
GBL, HIT, PMON_OUT, QREQ, TBST, TSIZ[0:2], TT[0:3],
TS, SHD[0:1], WT
0.5
0.5
0.5
0.5
0.5
0.5
–
–
–
ns
t
KHOE
SYSCLK to output enable
0.5
0.5
–
ns
t
KHOZ
SYSCLK to output high impedance (all except TS, ARTRY,
SHD0, SHD1)
–
–
3.5
ns
t
KHTSPZ
(3)(4)(5)
SYSCLK to TS high impedance after precharge
–
–
1
t
SYSCLK
t
KHARP
(3)(5)(6)(7)
Maximum delay to ARTRY/SHD0/SHD1 precharge
–
–
1
t
SYSCLK
t
KHARPZ
(3)(5)(6)(7)
SYSCLK to ARTRY/SHD0/SHD1 high impedance after
precharge
–
–
2
t
SYSCLK
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