參數(shù)資料
型號： PC7457MGU1200N
廠商： Atmel Corp.
英文描述： PowerPC 7457 RISC Microprocessor
中文描述： 7457的PowerPC RISC微處理器
文件頁數(shù)： 28/66頁
文件大?。?/td> 522K
代理商： PC7457MGU1200N
28
PC7457/47 [Preliminary]
5345B–HIREL–02/04
Notes:
1. Refer to the PC7450 RISC Microprocessor Family User’s Manual for specific information regarding L3OHCR.
2. See Table 13 on page 29 and Table 14 on page 32 for more information.
3. Guaranteed by design; not tested or characterized.
4. Default value.
5. Increasing values of L3CLKn_OH delay the L3_CLKn signal, effectively decreasing the output valid and output hold times of
all signals latched relative to that clock signal by the SRAM; see Figure 13 on page 30 and Figure 15 on page 33.
L3 Bus AC Specifications for
DDR MSUG2 SRAMs
When using DDR MSUG2 SRAMs at the L3 interface, the parts should be connected as
shown in Figure 13.
Outputs from the PC7457 are actually launched on the edges of an internal clock phase-
aligned to SYSCLK (adjusted for core and L3 frequency divisors). L3_CLK0 and
L3_CLK1 are this internal clock output with 90
°
phase delay, so outputs are shown syn-
chronous to L3_CLK0 and L3_CLK1. Output valid times are typically negative when
referenced to L3_CLKn because the data is launched one-quarter period before
L3_CLKn to provide adequate setup time at the SRAM after the delay-matched address,
control, data, and L3_CLKn signals have propagated across the printed-wiring board.
Inputs to the PC7457 are source-synchronous with the CQ clock generated by the DDR
MSUG2 SRAMs.
Table 12.
Effect of L3OHCR Settings on L3 Bus AC Timing
Field name
(1)
Affected Signals
Value
Output Valid Time
Output Hold Time
Unit
Notes
Parameter
Symbol
(2)
Change
(3)
Parameter
Symbol
(2)
Change
(3)
L3AOH
L3_ADDR[18:0],
L3_CNTL[0:1]
0b00
t
L3CHOV
0
t
L3CHOX
0
ps
(4)
0b01
+50
+50
0b10
+100
+100
0b11
+150
+150
L3CLKn_OH
All signals latched
by SRAM
connected to
L3_CLKn
0b000
t
L3CHOV
t
L3CHDV
t
L3CLDV
0
t
L3CHOX
t
L3CHDX
t
L3CLDX
0
(4)
0b001
-50
-50
(5)
0b010
-100
-100
(5)
0b011
-150
-150
(5)
0b100
-200
-200
(5)
0b101
-250
-250
(5)
0b110
-300
-300
(5)
0b111
-350
-350
(5)
L3DOHn
L3_DATA[n:n + 7],
L3_DP[n/8]
0b000
t
L3CHDV
t
L3CLDV
0
t
L3CHDX
t
L3CLDX
0
(4)
0b001
+50
+50
0b010
+100
+100
0b011
+150
+150
0b100
+200
+200
0b101
+250
+250
0b111
+350
+350
0b111
+350
+350
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