參數(shù)資料
型號(hào)： PC7457MGU933L
廠商： Atmel Corp.
英文描述： PowerPC 7457 RISC Microprocessor
中文描述： 7457的PowerPC RISC微處理器
文件頁(yè)數(shù)： 27/66頁(yè)
文件大?。?/td> 522K
代理商： PC7457MGU933L
27
PC7457/47 [Preliminary]
5345B–HIREL–02/04
Notes:
1. This specification describes a logical offset between the internal clock edge used to
launch the L3 address and control signals (this clock edge is phase-aligned with the
processor clock edge) and the internal clock edge used to launch the L3_CLK[n] sig-
nals. With proper board routing, this offset ensures that the L3_CLK[n] edge will
arrive at the SRAM within a valid address window and provide adequate setup and
hold time. This offset is reflected in the L3 bus interface AC timing specifications, but
must also be separately accounted for in the calculation of sample points and, thus, is
specified here.
2. This specification is the delay from a rising or falling edge on the internal_L3_CLK
signal to the corresponding rising or falling edge at the L3CLK[n] pins.
3. This specification is the delay from a rising or falling edge of L3_ECHO_CLK[n] to
data valid and ready to be sampled from the FIFO.
Effects of L3OHCR Settings on
L3 Bus AC Specifications
The AC timing of the L3 interface can be adjusted using the L3 Output Hold Control
Register (L3OCHR).
Each field controls the timing for a group of signals. The AC timing specifications pre-
sented herein represent the AC timing when the register contains the default value of
0x0000_0000. Incrementing a field delays the associated signals, increasing the output
valid time and hold time of the affected signals. In the special case of delaying an
L3_CLK signal, the net effect is to decrease the output valid and output hold times of all
signals being latched relative to that clock signal. The amount of delay added is summa-
rized in Table 12 on page 28.
Note that these settings affect output timing parameters only and
don’t
impact input tim-
ing parameters of the L3 bus in any way.
Table 11.
Sample Points Calculation Parameters
Symbol
Parameter
Max
Unit
t
AC
Delay from processor clock to internal_L3_CLK
(1)
3/4
t
L3_CLK
t
CO
Delay from internal_L3_CLK to L3_CLK[n] output pins
(2)
3
ns
t
ECI
Delay from L3_ECHO_CLK[n] to receive latch
(3)
3
ns
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