PC755B/745B
37/48
Table 16 shows the pin definitions.
Table 16. COP Pin Definitions
Pins
Signal
Connection
Special Notes
1
2
3
4
TDO
QACK
TDI
TRST
TDO
QACK
TDI
TRST
Add 2K pulldown to ground. Must be merged with on-board QACK, if any.
Add 2K pulldown to ground. Must be merged with on-board TRST, if any. See
Figure 23.
Used on 604e; leave no-connect for all other processors.
Add 2K pullup to OVDD (for short circuit limiting protection only).
5
6
RUN/STOP
VDD_SENSE
No Connect
VDD
7
8
TCK
CKSTP_IN
TCK
CKSTP_IN
Optional. Add 10K pullup to OVDD. Used on several emulator products. Useful for
checkstopping the processor from a logic analyzer of other external trigger.
9
10
11
TMS
N/A
SRESET
TMS
SRESET
Merge with on-board SRESET, if any.
12
13
14
15
16
N/A
HRESET
N/A
CKSTP_OUT
Ground
HRESET
Merge with on-board HRESET
.
Key location; pin should be removed.
Add 10K pullup to OVDD.
CKSTP_OUT
Digital Ground
5. PREPARATION FOR DELIVERY
5.1. Packaging
Microcircuits are prepared for delivery in accordance with MIL-PRF-38535 .
5.2. Certificate of compliance
TCS offers a certificate of compliances with each shipment of parts, affirming the products are in compliance either with MIL-PRF-883
and guarantiyng the parameters not tested at temperature extremes for the entire temperature range.
6. HANDLING
MOS devices must be handled with certain precautions to avoid damage due to accumulation of static charge. Input protection
devices have been designed in the chip to minimize the effect of static buildup. However, the following handling practices are recom-
mended:
a) Devices should be handled on benches with conductive and grounded surfaces.
b) Ground test equipment, tools and operator.
c) Do not handle devices by the leads.
d) Store devices in conductive foam or carriers.
e) Avoid use of plastic, rubber, or silk in MOS areas.
f) Maintain relative humidity above 50 percent if practical.
g) For CI-CGA packages, use specific tray to take care of the highest heigth of the package compared with the normal CBGA.