參數(shù)資料
型號(hào)： PC755CMGU300LE
廠商： ATMEL CORP
元件分類： 微控制器/微處理器
英文描述： PowerPC 755/745 RISC Microprocessor
中文描述： 32-BIT, 300 MHz, RISC PROCESSOR, CBGA360
封裝： CERAMIC, BGA-360
文件頁數(shù)： 34/50頁
文件大?。?/td> 1064K
代理商： PC755CMGU300LE
34
PC755/745
2138D–HIREL–06/03
Figure 22 provides the test access port timing diagram.
Figure 22.
Test Access Port Timing Diagram
JTAG Configuration Signals
Boundary scan testing is enabled through the JTAG interface signals. The TRST signal
is optional in the IEEE 1149.1 specification, but is provided on all processors that imple-
ment the PowerPC architecture. While it is possible to force the TAP controller to the
reset state using only the TCK and TMS signals, more reliable power-on reset perfor-
mance will be obtained if the TRST signal is asserted during power-on reset. Because
the JTAG interface is also used for accessing the common on-chip processor (COP)
function, simply tying TRST to HRESET is not practical.
The COP function of these processors allows a remote computer system (typically, a PC
with dedicated hardware and debugging software) to access and control the internal
operations of the processor. The COP interface connects primarily through the JTAG
port of the processor, with some additional status monitoring signals. The COP port
requires the ability to independently assert HRESET or TRST in order to fully control the
processor. If the target system has independent reset sources, such as voltage moni-
tors, watchdog timers, power supply failures, or push-button switches, then the COP
reset signals must bemerged into these signals with logic.
The arrangement shown in Figure 23 allows the COP port to independently assert
HRESET or TRST, while ensuring that the target can drive HRESET as well. If the JTAG
interface and COP header will not be used, TRST should be tied to HRESET through a
0
isolation resistor so that it is asserted when the systemreset signal (HRESET) is
asserted ensuring that the JTAG scan chain is initialized during power-on. While Motor-
ola recommends that the COP header be designed into the system as shown in Figure
23, if this is not possible, the isolation resistor will allow future access to TRST in the
casewhere a JTAG interfacemay need to be wired onto the system in debug situations.
The COP header shown in Figure 23 adds many benefits — breakpoints, watchpoints,
register and memory examination/modification, and other standard debugger features
are possible through this interface — and can be as inexpensive as an unpopulated
footprint for a header to be added when needed.
The COP interface has a standard header for connection to the target system, based on
the 0.025" square-post 0.100" centered header assembly (often called a Berg header).
The connector typically has pin 14 removed as a connector key.
TCK
TDI, TMS
TDO
VM
= Midpoint Voltage (OVDD/2)
TDO
VM
VM
tIXJH
tIVJH
tJLOV
tJLOH
tJLOZ
INPUT
DATA VALID
DATA
VALID
OUTPUT DATA VALID
相關(guān)PDF資料
PDF描述
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
PC755CMGU350LE 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:PowerPC 755/745 RISC Microprocessor
PC755CMGU366LE 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:PowerPC 755/745 RISC Microprocessor
PC755CMGU400LE 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:PowerPC 755/745 RISC Microprocessor
PC755CMZFU300LE 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:PowerPC 755/745 RISC Microprocessor
PC755CMZFU350LE 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:PowerPC 755/745 RISC Microprocessor
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