參數(shù)資料
型號: PC755CMZFU350LE
廠商: ATMEL CORP
元件分類: 微控制器/微處理器
英文描述: PowerPC 755/745 RISC Microprocessor
中文描述: 32-BIT, 350 MHz, RISC PROCESSOR, PBGA360
封裝: 25 X 25 MM, FLIP-CHIP, PLASTIC, BGA-360
文件頁數(shù): 46/50頁
文件大小: 1064K
代理商: PC755CMZFU350LE
46
PC755/745
2138D–HIREL–06/03
In addition, it is recommended that there be several bulk storage capacitors distributed
around the PCB, feeding the
V
DD
, L2O
V
DD
, and OV vplanes, to enable quick recharging
of the smaller chip capacitors. These bulk capacitors should have a low ESR (equivalent
series resistance) rating to ensure the quick response time necessary. They should also
be connected to the power and ground planes through two vias to minimize inductance.
Suggested bulk capacitors – 100-330 μF (AVX TPS tantalum or Sanyo OSCON).
Connection
Recommendations
To ensure reliable operation, it is highly recommended to connect unused inputs to an
appropriate signal level through a resistor. Unused active low inputs should be tied to
O
V
DD
. Unused active high inputs should be connected to GND. All NC (no-connect) sig-
nals must remain unconnected.
Power and ground connections must be made to all external
V
DD
, O
V
DD
, L2O
V
DD
, and
GND pins of the PC755.
Output Buffer DC Impedance
The PC755 60x and L2 I/O drivers are characterized over process, voltage, and temper-
ature. To measure Z
0
, an external resistor is connected from the chip pad to (L2)OV
DD
or
GND. Then, the value of each resistor is varied until the pad voltage is (L2)O
V
DD
/2 (See
Figure 33).
The output impedance is the average of two components, the resistances of the pull-up
and pull-down devices. When Data is held low, SW2 is closed (SW1 is open), and R
N
is
trimmed until the voltage at the pad equals (L2)O
V
DD
/2. R
N
then becomes the resistance
of the pull-down devices. When Data is held high, SW1 is closed (SW2 is open), and R
P
is trimmed until the voltage at the pad equals (L2)O
V
DD
/2. R
P
then becomes the resis-
tance of the pull-up devices.
NO TAG describes the driver impedance measurement circuit described above.
Figure 32.
Driver Impedance Measurement Circuit
(L2)OV
DD
OGND
R
P
R
N
Pad
Data
SW1
SW2
(L2)OV
DD
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