參數(shù)資料
型號(hào)： PC755CMZFU400LE
廠商： ATMEL CORP
元件分類： 微控制器/微處理器
英文描述： PowerPC 755/745 RISC Microprocessor
中文描述： 32-BIT, 400 MHz, RISC PROCESSOR, PBGA360
封裝： 25 X 25 MM, FLIP-CHIP, PLASTIC, BGA-360
文件頁(yè)數(shù)： 31/50頁(yè)
文件大小： 1064K
代理商： PC755CMZFU400LE
31
PC755/745
2138D–HIREL–06/03
Notes:
1. Rise and fall times for the L2SYNC_IN input are measured from 20% to 80% of L2OV
DD
.
2. All input specifications are measured from the midpoint of the signal in question to the midpoint voltage of the rising edge of
the input L2SYNC_IN (see Figure 8). Input timings are measured at the pins.
3. All output specifications are measured from the midpoint voltage of the rising edge of L2SYNC_IN to the midpoint of the sig-
nal in question. The output timings are measured at the pins. All output timings assume a purely resistive 50
load (See
Figure 10).
4. The outputs are valid for both single-ended and differential L2CLK modes. For pipelined registered synchronous Bur-
stRAMs, L2CR[14
-
15] = 01 or 10 is recommended. For pipelined late write synchronous BurstRAMs, L2CR[14
-
15] = 11 is
recommended.
5. Guaranteed by design and characterization.
6. Revisions prior to Rev 2.8 (Rev E) were limited in performance.and did not conform to this specification. Contact your local
Atmel sales office for more information.
Figure 15 shows the L2 bus input timing diagrams for the PC755.
Figure 15.
L2 Bus Input Timing Diagrams
Figure 16 shows the L2 bus output timing diagrams for the PC755.
Figure 16.
L2 Bus Output Timing Diagrams
Figure 17 provides the AC test load for L2 interface of the PC755.
Figure 17.
AC Test Load for the L2 Interface
L2SYNC_IN
L2 DATA AND DATA
PARITY INPUTS
VM
VM = Midpoint Voltage (L2OVDD/2)
t
DVL2CH
t
DXL2CH
t
L2CR
t
L2CF
L2SYNC_IN
ALL OUTPUTS
VM
VM = Midpoint Voltage (L2OVDD/2)
VM
L2DATA BUS
tL2CHOX
tL2CHOZ
tL2CHOV
OUTPUT
L2OVdd/2
R
L
= 50
Z
0
= 50
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