參數資料
型號: PC9RS08KA2PAE
廠商: Freescale Semiconductor
文件頁數: 68/136頁
文件大小: 0K
描述: MCU 8BIT 2KB FLASH RS08 8-DIP
標準包裝: 50
系列: RS08
核心處理器: RS08
芯體尺寸: 8-位
速度: 10MHz
外圍設備: LVD,POR,WDT
輸入/輸出數: 4
程序存儲器容量: 2KB(2K x 8)
程序存儲器類型: 閃存
RAM 容量: 63 x 8
電壓 - 電源 (Vcc/Vdd): 1.8 V ~ 5.5 V
振蕩器型: 內部
工作溫度: 0°C ~ 70°C
封裝/外殼: 8-DIP(0.300",7.62mm)
包裝: 管件
配用: DEMO9RS08KA2-ND - DEMO BOARD FOR 9RS08KA2
Chapter 5 Resets, Interrupts, and General System Control
MC9RS08KA2 Series Data Sheet, Rev. 4
Freescale Semiconductor
37
and ACMP are still available to wake the CPU from wait or stop mode. It is the responsibility of the user
application to poll the corresponding module to determine the source of wakeup.
Each wakeup source of the module is associated with a corresponding interrupt enable bit. If the bit is
disabled, the interrupt source is gated, and that particular source cannot wake the CPU from wait or stop
mode. However, the corresponding interrupt flag will still be set to indicate that an external wakeup event
has occurred.
The system interrupt pending register (SIP1) indicates the status of the system pending interrupt. When
the read-only bit of the SIP1 is enabled, it shows there is a pending interrupt to be serviced from the
indicated module. Writing to the register bit has no effect. The pending interrupt flag will be cleared
automatically when the all corresponding interrupt flags from the indicated module are cleared.
5.6
Low-Voltage Detect (LVD) System
The MC9RS08KA2 Series includes a system to protect against low voltage conditions in order to protect
memory contents and control MCU system states during supply voltage variations. The system is
comprised of a power-on reset (POR) circuit and an LVD circuit with a predefined trip voltage. The LVD
circuit is enabled with LVDE in SPMSC1. The LVD is disabled upon entering stop mode unless LVDSE
is set in SPMSC1. If LVDSE and LVDE are both set, the current consumption in stop with the LVD enabled
will be greater.
5.6.1
Power-On Reset Operation
When power is initially applied to the MCU, or when the supply voltage drops below the VPOR level, the
POR circuit will cause a reset condition. As the supply voltage rises, the LVD circuit will hold the MCU
in reset until the supply has risen above the VLVD level. Both the POR bit and the LVD bit in SRS are set
following a POR.
5.6.2
LVD Reset Operation
The LVD can be configured to generate a reset upon detection of a low voltage condition by setting
LVDRE to 1. After an LVD reset has occurred, the LVD system will hold the MCU in reset until the supply
voltage has risen above the level VLVD. The LVD bit in the SRS register is set following either an LVD
reset or POR.
5.6.3
LVD Interrupt Operation
When a low voltage condition is detected and the LVD circuit is configured using SPMSC1 for interrupt
operation (LVDE set, LVDIE set, and LVDRE clear), LVDF in SPMSC1 will be set and an LVD interrupt
request will occur.
5.7
Real-Time Interrupt (RTI)
The real-time interrupt function can be used to generate periodic interrupts. The RTI is driven from either
the 1-kHz internal clock reference or the trimmed 32-kHz internal clock reference from the ICS module.
The 32-kHz internal clock reference is divided by 32 by the RTI logic to produce a trimmed 1-kHz clock
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PC9RS08LA8CLF 功能描述:8位微控制器 -MCU 8-BIT 8K FLASH W/LCD RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數據總線寬度:8 bit 最大時鐘頻率:50 MHz 程序存儲器大小:16 KB 數據 RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風格:SMD/SMT
PC9RS08LE4CWL 功能描述:8位微控制器 -MCU 8-BIT 4K FLASH W/LCD RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數據總線寬度:8 bit 最大時鐘頻率:50 MHz 程序存儲器大小:16 KB 數據 RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風格:SMD/SMT
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