Figure 15. Deviation of DCO Output Across" />
參數(shù)資料
型號： PC9S08QE64CLH
廠商： Freescale Semiconductor
文件頁數(shù)： 16/50頁
文件大?。?/td> 0K
描述： MCU 8BIT 64K FLASH 64-LQFP
標準包裝： 160
系列： S08
核心處理器： S08
芯體尺寸： 8-位
速度： 50MHz
連通性： I²C，LIN，SCI，SPI
外圍設備： LVD，PWM，WDT
輸入/輸出數(shù)： 54
程序存儲器容量： 64KB（64K x 8）
程序存儲器類型： 閃存
RAM 容量： 4K x 8
電壓 - 電源 (Vcc/Vdd)： 1.8 V ~ 3.6 V
數(shù)據(jù)轉(zhuǎn)換器： A/D 22x12b
振蕩器型： 內(nèi)部
工作溫度： -40°C ~ 85°C
封裝/外殼： 64-LQFP
包裝： 托盤
Electrical Characteristics
MC9S08QE128 Series Data Sheet, Rev. 7
Freescale Semiconductor
23
Figure 15. Deviation of DCO Output Across Temperature at VDD = 3.0 V
8C
Total deviation of trimmed DCO output frequency over voltage
and temperature
Δfdco_t
—
+ 0.5
-1.0
± 2
%fdco
9C
Total deviation of trimmed DCO output frequency over fixed
voltage and temperature range of 0
°C to 70 °C
Δfdco_t
—
± 0.5
± 1
%fdco
10
C FLL acquisition time 3
tAcquire
——
1
ms
11
C
Long term jitter of DCO output clock (averaged over 2-ms
interval) 4
CJitter
—
0.02
0.2
%fdco
1 Data in Typical column was characterized at 3.0 V, 25°C or is typical recommended value.
2 The resulting bus clock frequency should not exceed the maximum specified bus clock frequency of the device.
3 This specification applies to any time the FLL reference source or reference divider is changed, trim value changed or changing
from FLL disabled (FBELP, FBILP) to FLL enabled (FEI, FEE, FBE, FBI). If a crystal/resonator is being used as the reference,
this specification assumes it is already running.
4 Jitter is the average deviation from the programmed frequency measured over the specified interval at maximum fBus.
Measurements are made with the device powered by filtered supplies and clocked by a stable external clock signal. Noise
injected into the FLL circuitry via VDD and VSS and variation in crystal oscillator frequency increase the CJitter percentage for a
given interval.
Table 12. ICS Frequency Specifications (Temperature Range = –40 to 85
°C Ambient) (continued)
Num C
Characteristic
Symbol
Min
Typ1
Max
Unit
-1.00%
-0.80%
-0.60%
-0.40%
-0.20%
0.00%
0.20%
0.40%
0.60%
-40
-20
0
20
40
60
80
100
120
VDD
%
deviation
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