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參數(shù)資料
| 型號： | PCA1465 |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | 32 kHz watch circuits with adaptive motor pulse |
| 中文描述： | 32千赫的自適應(yīng)電機(jī)脈沖手表電路 |
| 文件頁數(shù)： | 11/24頁 |
| 文件大?。?/td> | 132K |
| 代理商： | PCA1465 |
1998 Apr 21
11
Philips Semiconductors
Product specification
32 kHz watch circuits with adaptive motor
pulse
PCA146x series
Time calibration
Taking a normal quartz crystal with frequency 32768kHz,
frequency deviation (
f/f) of
±
15
×
10
6
and C
L
= 8.2 pF;
the oscillator frequency is offset (by using non-symmetrical
internal oscillator input and output capacitances of 10 pF
and 15 pF) such that the frequency deviation is
positive-only. This positive deviation can then be
compensated for to maintain time-keeping accuracy.
Once the positive frequency deviation is measured, a
corresponding number ‘n’ (see Table 2) can be
programmed into the device’s EEPROM. This causes n
pulses of frequency 8192 Hz to be inhibited every minute
of operation, which achieves the required calibration.
The programming circuit is shown in Fig.9. The required
number n is programmed into EEPROM by varying V
DD
according to the steps shown in Fig.10, which are
explained below:
1.
The positive quartz frequency deviation (
f/f) is
measured, and the corresponding values of n are
found according to Table 2.
2.
V
DD
is increased to 5.1 V allowing the contents of the
EEPROM to be checked from the motor pulse period
t
T3
at nominal frequency.
3.
V
DD
is decreased to 2.5 V during a motor pulse to
initialize a storing sequence.
The first V
DD
pulse to 5.1 V erases the contents of
EEPROM.
When the EEPROM is erased a logic 1 is at the TEST
pin.
V
DD
is increased to 5.1 V to read the data by pulsing
V
DD
n times to 4.5 V. After the n edge, V
DD
is
decreased to 2.5 V.
V
DD
is increased to 5.1 V to store n bits in the
EEPROM.
V
DD
is decreased to 2.5 V to terminate the storing
sequence and to return to operating mode.
V
DD
is increased to 5.1 V to check writing from the
motor pulse period t
T3
.
10. V
DD
is decreased to the operation voltage
between
two motor pulses to return to operating mode.
(Decreasing V
DD
during the motor pulse would restart
the programming mode).
4.
5.
6.
7.
8.
9.
The time calibration can be reprogrammed up to 100
times.
Table 2
Quartz crystal frequency deviation, n and t
T3
Notes
1.
2.
Increments of 2.03
×
10
6
/step.
Increments of 122
μ
s/step.
FREQUENCY
DEVIATION
f/f
(
×
10
6
)
0
(1)
+2.03
+4.06
.
.
.
+127.89
NUMBER OF
PULSES
(n)
t
T3
(ms)
0
1
2
.
.
.
31.250
(2)
31.372
31.494
.
.
.
38.936
63
Fig.9 Circuit for programming the time calibration.
MSA940
VDD
M1
M2
RESET
VSS
TEST
OSC IN
OSC OUT
M
PCA146x
SERIES
1
2
3
4
8
7
6
5
32 kHz
SIGNAL GENERATOR
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