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參數(shù)資料
| 型號： | PCA9500PW,118 |
| 廠商： | NXP Semiconductors |
| 文件頁數(shù)： | 8/26頁 |
| 文件大小： | 0K |
| 描述： | IC I/O EXPANDER I2C 8B 16TSSOP |
| 標準包裝： | 2,500 |
| 接口： | I²C，SM 總線 |
| 輸入/輸出數(shù)： | 8 |
| 中斷輸出： | 無 |
| 頻率 - 時鐘： | 400kHz |
| 電源電壓： | 2.5 V ~ 3.6 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 16-TSSOP（0.173"，4.40mm 寬） |
| 供應商設(shè)備封裝： | 16-TSSOP |
| 包裝： | 帶卷 (TR) |
| 包括： | EEPROM，POR |
| 其它名稱： | 935271534118 PCA9500PW-T PCA9500PW-T-ND |
PCA9500_4
NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 04 — 15 April 2009
16 of 26
NXP Semiconductors
PCA9500
8-bit I2C-bus and SMBus I/O port with 2-kbit EEPROM
12. Dynamic characteristics
[1]
All the timing values are valid within the operating supply voltage and ambient temperature range and refer to VIL and VIH with an input
voltage swing of VSS to VDD.
[2]
tpu(R) and tpu(W) are the delays required from the time VDD is stable until the specied operation can be initiated. These parameters are
guaranteed by design.
[3]
Tcy(W) is the maximum time that the device requires to perform the internal write operation.
Table 6.
Dynamic characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
fSCL
SCL clock frequency
-
400
kHz
tSP
pulse width of spikes that must be
suppressed by the input lter
-
50
ns
tBUF
bus free time between a STOP and START
condition
1.3
-
s
tSU;STA
set-up time for a repeated START condition
0.6
-
s
tHD;STA
hold time (repeated) START condition
0.6
-
s
tr
rise time of both SDA and SCL signals
-
0.3
s
tf
fall time of both SDA and SCL signals
-
0.3
s
tSU;DAT
data set-up time
250
-
ns
tHD;DAT
data hold time
0
-
ns
tVD;DAT
data valid time
SCL LOW to
data output
-
1.0
s
tSU;STO
set-up time for STOP condition
0.6
-
s
Port timing
tv(Q)
data output valid time
CL ≤ 100 pF
-
4
s
tsu(D)
data input set-up time
CL ≤ 100 pF
0
-
s
th(D)
data input hold time
CL ≤ 100 pF
4
-
s
Power-up timing
tpu(R)
read power-up time
[2] --1
ms
tpu(W)
write power-up time
[2] --5
ms
Write cycle limits (see Figure 23)
Tcy(W)
write cycle time
[3] -
5
10
ms
Table 7.
Non-volatile storage specications
Parameter
Specication
memory cell data retention
10 years minimum
number of memory cell write cycles
100,000 cycles minimum
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