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參數(shù)資料
| 型號(hào)： | PCA9502BS,157 |
| 廠商： | NXP Semiconductors |
| 文件頁數(shù)： | 22/25頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC I/O EXPANDER I2C/SPI 24HVQFN |
| 標(biāo)準(zhǔn)包裝： | 2,450 |
| 接口： | I²C，SPI |
| 輸入/輸出數(shù)： | 8 |
| 中斷輸出： | 無 |
| 頻率 - 時(shí)鐘： | 400kHz |
| 電源電壓： | 2.3 V ~ 3.6 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 24-VFQFN 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 24-HVQFN（4x4） |
| 包裝： | 托盤 |
| 其它名稱： | 935281363157 PCA9502BS PCA9502BS-ND |
PCA9502_3
NXP B.V. 2006. All rights reserved.
Product data sheet
Rev. 03 — 13 October 2006
6 of 25
NXP Semiconductors
PCA9502
8-bit I/O expander with I2C-bus/SPI interface
8.2 Programmable I/O pins State register (IOState)
When ‘read’, this register returns the actual state of all I/O pins. When ‘write’, each
register bit will be transferred to the corresponding IO pin programmed as output.
8.3 I/O Interrupt Enable register (IOIntEna)
This register enables the interrupt due to a change in the I/O congured as inputs.
8.4 I/O Control register (IOControl)
Table 8.
IOState register (address 0x0B) bit description
Bit
Symbol
Description
7:0
IOState
Write this register: set the logic level on the output pins
0 = set output pin to zero
1 = set output pin to one
Read this register: return states of all pins
Table 9.
IOIntEna register (address 0x0C) bit description
Bit
Symbol
Description
7:0
IOIntEna
input interrupt enable
0 = a change in the input pin will not generate an interrupt
1 = a change in the input will generate an interrupt
Table 10.
IOControl register (address 0x0E) bit description
Bit
Symbol
Description
7:4
-
reserved for future use
3
SReset
software reset
A write to this bit will reset the device. Once the device is reset this
bit is automatically set to 0.
2:1
-
reserved for future use
0
IOLatch
enable/disable inputs latching
0 = input values are not latched. A change in any input generates an
interrupt. A read of the input register clears the interrupt. If the input
goes back to its initial logic state before the input register is read,
then the interrupt is cleared.
1 = input values are latched. A change in the input generates an
interrupt and the input logic value is loaded in the bit of the
corresponding input state register (IOState). A read of the IOState
register clears the interrupt. If the input pin goes back to its initial
logic state before the interrupt register is read, then the interrupt is
not cleared and the corresponding bit of the IOState register keeps
the logic value that initiates the interrupt.
Example: If GPIO4 input was as logic 0 and the input goes to logic 1
then back to logic 0, the IOState register will capture this change and
an interrupt is generated (if enabled). When the read is performed on
the IOState register, the interrupt is de-asserted, assuming there were
no additional input(s) that changed, and bit 4 of the IOState register
will read ‘1’. The next read of the IOState register should now read ‘0’.
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