參數(shù)資料
型號： PCA9505DGG,118
廠商： NXP Semiconductors
文件頁數(shù)： 4/34頁
文件大?。?/td> 0K
描述： IC I/O EXPANDER I2C 40B 56TSSOP
標(biāo)準(zhǔn)包裝： 2,000
接口： I²C
輸入/輸出數(shù)： 40
中斷輸出： 是
頻率 - 時鐘： 400kHz
電源電壓： 2.3 V ~ 5.5 V
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 56-TFSOP（0.240"，6.10mm 寬）
供應(yīng)商設(shè)備封裝： 56-TSSOP
包裝： 帶卷 (TR)
包括： POR
其它名稱： 935284486118
PCA9505DGG-T
PCA9505DGG-T-ND
PCA9505_9506
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 4 — 3 August 2010
12 of 34
NXP Semiconductors
PCA9505/06
40-bit I2C-bus I/O port with RESET, OE and INT
7.3.4 IOC0 to IOC4 - I/O Configuration registers
These registers configure the direction of the I/O pins.
Cx[y] = 0: The corresponding port pin is an output.
Cx[y] = 1: The corresponding port pin is an input.
Where ‘x’ refers to the bank number (0 to 4); ‘y’ refers to the bit number (0 to 7).
7.3.5 MSK0 to MSK4 - Mask interrupt registers
These registers mask the interrupt due to a change in the I/O pins configured as inputs.
‘x’ refers to the bank number (0 to 4); ‘y’ refers to the bit number (0 to 7).
Mx[y] = 0: A level change at the I/O will generate an interrupt if IOx_y defined as input
(Cx[y] in IOC register = 1).
Mx[y] = 1: A level change in the input port will not generate an interrupt if IOx_y defined
as input (Cx[y] in IOC register = 1).
7.4 Power-on reset
When power is applied to VDD, an internal Power-On Reset (POR) holds the PCA9505/06
in a reset condition until VDD has reached VPOR. At that point, the reset condition is
released and the PCA9505/06 registers and I2C-bus state machine will initialize to their
default states. Thereafter, VDD must be lowered below 0.2 V to reset the device.
7.5 RESET input
A reset can be accomplished by holding the RESET pin LOW for a minimum of tw(rst). The
PCA9505/06 registers and I2C-bus state machine will be held in their default states until
the RESET input is once again HIGH.
Table 7.
IOC0 to IOC4 - I/O Configuration registers (address 18h to 1Ch) bit description
Legend: * default value.
Address
Register
Bit
Symbol
Access
Value
Description
18h
IOC0
7 to 0
C0[7:0]
R/W
1111 1111*
I/O Configuration register bank 0
19h
IOC1
7 to 0
C1[7:0]
R/W
1111 1111*
I/O Configuration register bank 1
1Ah
IOC2
7 to 0
C2[7:0]
R/W
1111 1111*
I/O Configuration register bank 2
1Bh
IOC3
7 to 0
C3[7:0]
R/W
1111 1111*
I/O Configuration register bank 3
1Ch
IOC4
7 to 0
C4[7:0]
R/W
1111 1111*
I/O Configuration register bank 4
Table 8.
MSK0 to MSK4 - Mask interrupt registers (address 20h to 24h) bit description
Legend: * default value.
Address
Register
Bit
Symbol
Access
Value
Description
20h
MSK0
7 to 0
M0[7:0]
R/W
1111 1111*
Mask Interrupt register bank 0
21h
MSK1
7 to 0
M1[7:0]
R/W
1111 1111*
Mask Interrupt register bank 1
22h
MSK2
7 to 0
M2[7:0]
R/W
1111 1111*
Mask Interrupt register bank 2
23h
MSK3
7 to 0
M3[7:0]
R/W
1111 1111*
Mask Interrupt register bank 3
24h
MSK4
7 to 0
M4[7:0]
R/W
1111 1111*
Mask Interrupt register bank 4
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