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| 型號(hào)： | PCA9506DGG,512 |
| 廠商： | NXP Semiconductors |
| 文件頁數(shù)： | 32/34頁 |
| 文件大小： | 0K |
| 描述： | IC I/O EXPANDER I2C 40B 56TSSOP |
| 產(chǎn)品培訓(xùn)模塊： | I²C Bus Fundamentals |
| 特色產(chǎn)品： | NXP - I2C Interface |
| 標(biāo)準(zhǔn)包裝： | 35 |
| 接口： | I²C |
| 輸入/輸出數(shù)： | 40 |
| 中斷輸出： | 是 |
| 頻率 - 時(shí)鐘： | 400kHz |
| 電源電壓： | 2.3 V ~ 5.5 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 56-TFSOP（0.240"，6.10mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 56-TSSOP |
| 包裝： | 管件 |
| 包括： | POR |
| 產(chǎn)品目錄頁面： | 824 (CN2011-ZH PDF) |
| 其它名稱： | 568-3354-5 935280798512 PCA9506DGG |
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PCA9505_9506
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 4 — 3 August 2010
7 of 34
NXP Semiconductors
PCA9505/06
40-bit I2C-bus I/O port with RESET, OE and INT
[1]
HVQFN56 package die supply ground is connected to both VSS pins and exposed center pad. VSS pins
must be connected to supply ground for proper device operation. For enhanced thermal, electrical, and
board level performance, the exposed pad needs to be soldered to the board using a corresponding
thermal pad on the board and for proper heat conduction through the board, thermal vias need to be
incorporated in the printed-circuit board in the thermal pad region.
7.
Functional description
7.1 Device address
Following a START condition, the bus master must send the address of the slave it is
accessing and the operation it wants to perform (read or write). The address of the
PCA9505/06 is shown in Figure 5. Slave address pins A2, A1, and A0 choose 1 of 8 slave
addresses and need to be connected to VDD (1) or VSS (0). To conserve power, no internal
pull-up resistors are incorporated on A2, A1, and A0.
The last bit of the first byte defines the operation to be performed. When set to logic 1 a
read is selected, while a logic 0 selects a write operation.
7.2 Command register
Following the successful acknowledgement of the slave address + R/W bit, the bus
master will send a byte to the PCA9505/06, which will be stored in the Command register.
OE
30
23
I
active LOW output enable input
INT
55
48
O
active LOW interrupt output
RESET
56
49
I
active LOW reset input
Table 2.
Pin description …continued
Symbol
Pin
Type
Description
TSSOP56
HVQFN56
Fig 5.
PCA9505/06 address
002aab494
0
1
0
A2
A1
A0 R/W
fixed
slave address
programmable
Fig 6.
Command register
002aab495
1
0
AI
D5
D4
D3
D2
D1
D0
Auto-Increment
register number
default at power-up
or after RESET
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