I2C-bus: The serial revolution By replacing complex parallel interfaces with a s" />
參數(shù)資料
型號: PCA9509AGM,125
廠商: NXP Semiconductors
文件頁數(shù): 2/8頁
文件大小: 0K
描述: IC I2C BUS/SMBUS REPEATER 8-XQFN
特色產(chǎn)品: NXP - I2C Interface
標準包裝: 1
系列: *
其它名稱: 568-9472-6
I2C-bus: The serial revolution
By replacing complex parallel interfaces with a straightforward yet powerful serial
structure, the I2C-bus revolutionized chip-to-chip communications.
Invented by NXP (Philips) more than 30 years ago, the I2C-bus uses a simple two-wire
format to carry data one bit at a time. It performs inter-chip addressing, selection,
control, and data transfer. Speeds are up to 400 kHz (Fast-mode), 1 MHz (Fast-mode
Plus), 3.4 MHz (High Speed-mode), or 5 MHz (Ultra Fast-mode).
The I2C-bus shrinks the IC footprint and leads to lower IC costs. Plus, since far fewer
copper traces are needed, it enables a smaller PCB, reduces design complexity, and
lowers system cost.
SDA
SCL
uC
A0
A1
1010A2A1A0R/W
A2
New function address
1010011 R/W
New function address
as assigned
New
function
MCU
RTC
LCD
I/O
A/D
D/A
I2C-bus devices are available in a wide range of functions. Each slave device has its own I2C-bus address, selectable using
address pins set high (1) or low (0). Information is transmitted byte by byte, and each byte is acknowledged by the receiver.
There can be multiple devices on the same bus, and more than one IC can act as master. The master role is typically played by a
microcontroller.
Parallel Interface
I2C Serial Interface
Master
Write data
Slave
SDA
SCL
transmitter
P
W
S
data
slave address
data
A
receiver
SDA
SCL
transmitter
receiver
Read data
P
R
S
data
slave address
data
A
<
n data bytes
>
last data byte
S = Start condition
R/W = read/write
A = Acknowledge
A = Not acknowledge P = Stop condition
The master always sends the clock
< n data >
bytes
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