參數(shù)資料
型號: PCA9530D
廠商: NXP Semiconductors N.V.
元件分類: LED驅(qū)動器
英文描述: 2-bit I2C-bus LED dimmer
封裝: PCA9530D<SOT96-1 (SO8)|<<http://www.nxp.com/packages/SOT96-1.html<1<week 5, 2005,;PCA9530D<SOT96-1 (SO8)|<<http://www.nxp.com/packages/SOT96-1.html<1<week 5, 2005,;
文件頁數(shù): 23/24頁
文件大?。?/td> 143K
代理商: PCA9530D
PCA9530_3
NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 03 — 26 February 2009
8 of 24
NXP Semiconductors
PCA9530
2-bit I2C-bus LED dimmer
7.2 System conguration
A device generating a message is a ‘transmitter’; a device receiving is the ‘receiver’. The
device that controls the message is the ‘master’ and the devices which are controlled by
the master are the ‘slaves’ (see Figure 8).
7.3 Acknowledge
The number of data bytes transferred between the START and the STOP conditions from
transmitter to receiver is not limited. Each byte of eight bits is followed by one
acknowledge bit. The acknowledge bit is a HIGH level put on the bus by the transmitter,
whereas the master generates an extra acknowledge related clock pulse.
A slave receiver which is addressed must generate an acknowledge after the reception of
each byte. Also a master must generate an acknowledge after the reception of each byte
that has been clocked out of the slave transmitter. The device that acknowledges has to
pull down the SDA line during the acknowledge clock pulse, so that the SDA line is stable
LOW during the HIGH period of the acknowledge related clock pulse; set-up and hold
times must be taken into account.
A master receiver must signal an end of data to the transmitter by not generating an
acknowledge on the last byte that has been clocked out of the slave. In this event, the
transmitter must leave the data line HIGH to enable the master to generate a STOP
condition.
Fig 8.
System conguration
002aaa966
MASTER
TRANSMITTER/
RECEIVER
SLAVE
RECEIVER
SLAVE
TRANSMITTER/
RECEIVER
MASTER
TRANSMITTER
MASTER
TRANSMITTER/
RECEIVER
SDA
SCL
I2C-BUS
MULTIPLEXER
SLAVE
Fig 9.
Acknowledgement on the I2C-bus
002aaa987
S
START
condition
9
8
2
1
clock pulse for
acknowledgement
not acknowledge
acknowledge
data output
by transmitter
data output
by receiver
SCL from master
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