參數(shù)資料
型號: PCA9554TS,118
廠商: NXP Semiconductors
文件頁數(shù): 2/35頁
文件大?。?/td> 0K
描述: IC I/O EXPANDER I2C 8B 20SSOP
標(biāo)準(zhǔn)包裝: 1
接口: I²C,SM 總線
輸入/輸出數(shù): 8
中斷輸出:
頻率 - 時鐘: 400kHz
電源電壓: 2.3 V ~ 5.5 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 20-LSSOP(0.173",4.40mm 寬)
供應(yīng)商設(shè)備封裝: 20-SSOP
包裝: 剪切帶 (CT)
包括: POR
其它名稱: 568-2026-1
PCA9554_9554A
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 9 — 19 March 2013
10 of 35
NXP Semiconductors
PCA9554; PCA9554A
8-bit I2C-bus and SMBus I/O port with interrupt
6.5 Device address
6.6 Bus transactions
Data is transmitted to the PCA9554/PCA9554A registers using the Write mode as shown
in Figure 11 and Figure 12. Data is read from the PCA9554/PCA9554A registers using the
Read mode as shown in Figure 13 and Figure 14. These devices do not implement an
auto-increment function, so once a command byte has been sent, the register which was
addressed will continue to be accessed by reads until a new command byte has been
sent.
Fig 9.
PCA9554 device address
Fig 10. PCA9554A device address
002aac494
0
1
0
A2
A1
A0 R/W
fixed
slave address
hardware
selectable
002aac495
0
1
A2
A1
A0 R/W
fixed
slave address
hardware
selectable
Fig 11. Write to Output Port register
1
0
A2 A1 A0
0
A
S0
START condition
R/W
acknowledge
from slave
002aac472
A
acknowledge
from slave
SCL
SDA
A
write to port
data out
from port
P
tv(Q)
9
8
7
6
5
4
3
2
1
command byte
acknowledge
from slave
data to port
DATA 1
slave address
0000001
0
STOP
condition
data 1 valid
Fig 12. Write to Configuration register or Polarity Inversion register
1
0
A2 A1 A0
0
A
S0
START condition
R/W
acknowledge
from slave
002aac473
A
acknowledge
from slave
SCL
SDA
A
data to
register
P
9
8
7
6
5
4
3
2
1
command byte
acknowledge
from slave
data to register
DATA
slave address
000001 1/0
0
STOP
condition
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