參數(shù)資料
型號(hào): PCA9561
廠商: NXP Semiconductors N.V.
英文描述: Quad 6-bit multiplexed I2C EEPROM DIP switch
中文描述: 四6位多路復(fù)用的I2C EEPROM的DIP開(kāi)關(guān)
文件頁(yè)數(shù): 12/17頁(yè)
文件大小: 111K
代理商: PCA9561
Philips Semiconductors
Product data
PCA9561
Quad 6-bit multiplexed I
2
C EEPROM DIP switch
2003 Jun 27
12
AC CHARACTERISTICS
LIMITS
TYP.
SYMBOL
PARAMETER
MIN.
MAX.
UNIT
MUX_IN
MUX_OUT
t
PLH
t
PHL
Select
MUX_OUT
t
PLH
t
PHL
t
R
t
F
C
L
LOW-to-HIGH transition time
28
40
ns
HIGH-to-LOW transition time
8
15
ns
LOW-to-HIGH transition time
30
43
ns
HIGH-to-LOW transition time
10
15
ns
Output rise time
1.0
3
ns/V
Output fall time
1.0
3
ns/V
Test load capacitance on outputs
pF
SYMBOL
PARAMETER
STANDARD-MODE
I
2
C-BUS
MIN
0
4.7
FAST-MODE I
2
C-BUS
UNIT
MAX
100
MIN
0
1.3
MAX
400
f
SCL
t
BUF
SCL clock frequency
Bus free time between a STOP and START condition
Hold time (repeated) START condition
After this period, the first clock pulse is generated
LOW period of the SCL clock
HIGH period of the SCL clock
Set-up time for a repeated START condition
Data hold time
Data set-up time
Rise time of both SDA and SCL signals
Fall time of both SDA and SCL signals
Set-up time for STOP condition
Capacitive load for each bus line
Pulse width of spikes which must be suppressed
by the input filter
kHz
μ
s
t
HD;STA
4.0
0.6
μ
s
t
LOW
t
HIGH
t
SU;STA
t
HD;DAT
t
SU;DAT
t
r
t
f
t
SU;STO
C
b
4.7
4.0
4.7
0
1
250
4.0
3.45
1000
300
400
1.3
0.6
0.6
0
1
100
0.9
300
300
400
μ
s
μ
s
μ
s
μ
s
ns
ns
ns
μ
s
pF
20 + 0.1C
b2
20 + 0.1C
b2
0.6
t
SP
50
50
ns
NOTES:
1. A device must internally provide a hold time of at least 300 ns for the SDA signal (referred to the V
IH(min)
of the SCL signal) in order to bridge
the undefined region of the falling edge of SCL.
2. C
b
= total capacitance of one bus line in pF.
t
SP
t
BUF
t
HD;STA
P
P
S
t
LOW
t
R
t
HD;DAT
t
F
t
HIGH
t
SU;DAT
t
SU;STA
Sr
t
HD;STA
t
SU;STO
SDA
SCL
SU00645
Figure 10. Definition of timing
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