參數(shù)資料
型號： PCA9574PW,112
廠商： NXP Semiconductors
文件頁數(shù)： 2/33頁
文件大?。?/td> 0K
描述： IC I/O EXPANDER I2C 8B 16TSSOP
標(biāo)準(zhǔn)包裝： 96
接口： I²C，SM 總線
輸入/輸出數(shù)： 8
中斷輸出： 是
頻率 - 時鐘： 400kHz
電源電壓： 1.1 V ~ 3.6 V
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 16-TSSOP（0.173"，4.40mm 寬）
供應(yīng)商設(shè)備封裝： 16-TSSOP
包裝： 帶卷 (TR)
包括： POR
其它名稱： 935285149112
PCA9574PW
PCA9574PW-ND
PCA9574
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 4 — 25 April 2012
10 of 33
NXP Semiconductors
PCA9574
8-bit I2C-bus and SMBus, level translating, low volage GPIO
7.5.4 Register 3 - Pull-up/pull-down selector register
When bus-hold feature is not selected and bit 1 of Register 2 is set to logic 1, the I/O port
can be configured to have pull-up or pull-down by programming the pull-up/pull-down
register. Setting a bit to logic 1 will select a 100 k
Ω pull-up resistor for that I/O pin. Setting
a bit to logic 0 will select a 100 k
Ω pull-down resistor for that I/O pin. If the bus-hold
feature is enabled, writing to this register will have no effect on pull-up/pull-down
selection.
7.5.5 Register 4 - Configuration register
This register configures the direction of the I/O pins. If a bit in this register is set (written
with logic 1), the corresponding port pin is enabled as an input with high-impedance
output driver. If a bit in this register is cleared (written with logic 0), the corresponding port
pin is enabled as an output. At reset, the device’s ports are inputs.
Table 8.
Register 3 - Pull-up/pull-down selector register (address 03h) bit description
Legend: * default value.
Bit
Symbol
Access
Value
Description
7
P0.7
R/W
1*
configures I/O port pin to have pull-up or pull-down when
bus-hold feature not selected and bit 1 of Register 2 is
logic 1
0 = selects a 100 k
Ω pull-down resistor for that I/O pin
1 = selects a 100 k
Ω pull-up resistor for that I/O pin
(default value)
6P0.6
R/W
1*
5P0.5
R/W
1*
4P0.4
R/W
1*
3P0.3
R/W
1*
2P0.2
R/W
1*
1P0.1
R/W
1*
0P0.0
R/W
1*
Table 9.
Register 4 - Configuration register (address 04h) bit description
Legend: * default value.
Bit
Symbol
Access
Value
Description
7
C0.7
R/W
1*
configures the direction of the I/O pins
0 = corresponding port pin enabled as an output
1 = corresponding port pin configured as input
(default value)
6
C0.6
R/W
1*
5
C0.5
R/W
1*
4
C0.4
R/W
1*
3
C0.3
R/W
1*
2
C0.2
R/W
1*
1
C0.1
R/W
1*
0
C0.0
R/W
1*
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