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參數(shù)資料
| 型號： | PCA9655EDTR2G |
| 廠商： | ON Semiconductor |
| 文件頁數(shù)： | 5/20頁 |
| 文件大小： | 0K |
| 描述： | IC I/O EXPANDER I2C 16B 24-TSSOP |
| 標準包裝： | 1 |
| 接口： | I²C 總線，SM 總線 |
| 輸入/輸出數(shù)： | 16 |
| 中斷輸出： | 是 |
| 頻率 - 時鐘： | 100kHz |
| 電源電壓： | 1.65 V ~ 5.5 V |
| 工作溫度： | -55°C ~ 125°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 24-TSSOP（0.173"，4.40mm 寬） |
| 供應商設(shè)備封裝： | 24-TSSOP |
| 包裝： | 標準包裝 |
| 其它名稱： | PCA9655EDTR2GOSDKR |
PCA9655E
http://onsemi.com
13
Figure 10. Read from Input Port Register, Scenario 2
Remark: Transfer of data can be stopped at any moment by a STOP condition. When this occurs, data present at the latest acknowledge
phase is valid (output mode). It is assumed that the command byte has previously been set to ’00’ (read Input Port register).
A2 A1 A0 1 A
S A6
START condition
R/W
acknowledge
from slave
A
SCL
SDA
A
read from port 0
P
9
8
7
6
5
4
3
2
1
I0.x
slave address
STOP condition
acknowledge
from master
A
I1.x
acknowledge
from master
A
I0.x
acknowledge
from master
1
I1.x
non acknowledge
from master
data into port 0
read from port 1
data into port 1
INT
tv(INT_N)
t rst(INT_N)
2
1
A
T
A
D
3
0
A
T
A
D
0
1
A
T
A
D
0
A
T
A
D
DATA 00
DATA 01
th(D)
DATA 02
tsu(D)
DATA 03
tsu(D)
2
1
A
T
A
D
1
A
T
A
D
0
1
A
T
A
D
A5A4 A3
Interrupt Output
The opendrain interrupt output is activated when an I/O
pin configured as an input changes state. The interrupt is
deactivated when the input pin returns to its previous state
or when the Input Port register is read (see Figure 9). A pin
configured as an output cannot cause an interrupt. Since
each 8bit port is read independently, the interrupt caused by
Port 0 will not be cleared by a read of Port 1 or the other way
around.
Remark: Changing an I/O from an output to an input may
cause a false interrupt to occur if the state of the pin does not
match the contents of the Input Port register.
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