參數(shù)資料
型號: PCA9671BS,118
廠商: NXP Semiconductors
文件頁數(shù): 15/33頁
文件大?。?/td> 0K
描述: IC I/O EXPANDER I2C 16B 24HVQFN
特色產(chǎn)品: NXP - I2C Interface
標(biāo)準(zhǔn)包裝: 1
接口: I²C
輸入/輸出數(shù): 16
中斷輸出:
頻率 - 時鐘: 1MHz
電源電壓: 2.3 V ~ 5.5 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 24-VFQFN 裸露焊盤
供應(yīng)商設(shè)備封裝: 24-HVQFN(4x4)
包裝: 標(biāo)準(zhǔn)包裝
包括: POR
其它名稱: 568-8718-6
PIC16(L)F1526/27
DS41458A-page 22
Preliminary
2011 Microchip Technology Inc.
3.2
Data Memory Organization
The data memory is partitioned in 32 memory banks
with 128 bytes in a bank. Each bank consists of
12 core registers
20 Special Function Registers (SFR)
Up to 80 bytes of General Purpose RAM (GPR)
16 bytes of common RAM
The active bank is selected by writing the bank number
into the Bank Select Register (BSR). Unimplemented
memory will read as ‘0’. All data memory can be
accessed either directly (via instructions that use the
file registers) or indirectly via the two File Select
Registers
(FSR).
See
for more information.
Data memory uses a 12-bit address. The upper 7-bit of
the address define the Bank address and the lower
5-bits select the registers/RAM in that bank.
3.2.1
CORE REGISTERS
The core registers contain the registers that directly
affect the basic operation. The core registers occupy
the first 12 addresses of every data memory bank
(addresses x00h/x08h through x0Bh/x8Bh). These
registers are listed below in Table 3-2. For detailed
information, see Table 3-4.
TABLE 3-2:
CORE REGISTERS
Addresses
BANKx
x00h or x80h
INDF0
x01h or x81h
INDF1
x02h or x82h
PCL
x03h or x83h
STATUS
x04h or x84h
FSR0L
x05h or x85h
FSR0H
x06h or x86h
FSR1L
x07h or x87h
FSR1H
x08h or x88h
BSR
x09h or x89h
WREG
x0Ah or x8Ah
PCLATH
x0Bh or x8Bh
INTCON
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