參數(shù)資料
型號： PCA9698DGG/S911,51
廠商： NXP Semiconductors
文件頁數(shù)： 31/48頁
文件大?。?/td> 0K
描述： IC I/O EXPANDER I2C 40B 56TSSOP
標(biāo)準(zhǔn)包裝： 2,000
接口： I²C
輸入/輸出數(shù)： 40
中斷輸出： 是
頻率 - 時鐘： 1MHz
電源電壓： 2.3 V ~ 5.5 V
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 56-TFSOP（0.240"，6.10mm 寬）
供應(yīng)商設(shè)備封裝： 56-TSSOP
包裝： 帶卷 (TR)
包括： POR
其它名稱： 935285491518
PCA9698DGG/S911-T
PCA9698DGG/S911-T-ND
37
7810C–AVR–10/12
Atmel ATmega328P [Preliminary]
9.
Power Management and Sleep Modes
Sleep modes enable the application to shut down unused modules in the MCU, thereby saving
power. The AVR provides various sleep modes allowing the user to tailor the power consump-
tion to the application’s requirements.
When enabled, the Brown-out Detector (BOD) actively monitors the power supply voltage during
the sleep periods. To further save power, it is possible to disable the BOD in some sleep modes.
See “BOD Disable” on page 38 for more details.
9.1
Sleep Modes
Figure 8-1 on page 25 presents the different clock systems in the ATmega328P, and their distri-
bution. The figure is helpful in selecting an appropriate sleep mode. Table 9-1 shows the
different sleep modes, their wake up sources BOD disable ability.
Notes:
1. Only recommended with external crystal or resonator selected as clock source.
2. If Timer/Counter2 is running in asynchronous mode.
3. For INT1 and INT0, only level interrupt.
To enter any of the six sleep modes, the SE bit in SMCR must be written to logic one and a
SLEEP instruction must be executed. The SM2, SM1, and SM0 bits in the SMCR Register select
which sleep mode (Idle, ADC Noise Reduction, Power-down, Power-save, Standby, or Extended
Standby) will be activated by the SLEEP instruction. See Table 9-2 on page 42 for a summary.
If an enabled interrupt occurs while the MCU is in a sleep mode, the MCU wakes up. The MCU
is then halted for four cycles in addition to the start-up time, executes the interrupt routine, and
resumes execution from the instruction following SLEEP. The contents of the Register File and
SRAM are unaltered when the device wakes up from sleep. If a reset occurs during sleep mode,
the MCU wakes up and executes from the Reset Vector.
Table 9-1.
Active Clock Domains and Wake-up Sources in the Different Sleep Modes.
Active Clock Domains
Oscillators
Wake-up Sources
Softw
are
BOD
Disab
le
Sleep Mode
clk
CPU
clk
FL
A
S
H
clk
IO
clk
ADC
clk
ASY
Ma
in
Cl
o
c
k
Sourc
e
Enab
led
Timer
Oscillator
Enab
led
INT1,
INT
0
and
Pin
Ch
ang
e
TWI
Ad
dress
Match
Timer2
SPM/EEPR
OM
Re
ady
ADC
WDT
Ot
her/
O
Idle
XXX
X
X
XXX
ADC Noise
Reduction
XX
X
XX(2)
XX
X
Power-down
XX
X
Power-save
X
XX
X
Standby(1)
XX
X
Extended
Standby
XX
X
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