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參數(shù)資料
| 型號(hào)： | PCB2421P |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | PROM |
| 英文描述： | 1K dual mode serial EEPROM |
| 中文描述： | I2C/2-WIRE SERIAL EEPROM, PDIP8 |
| 封裝： | 0.300 MIL, PLASTIC, MO-001-AN, SOT-97-1, DIP-8 |
| 文件頁(yè)數(shù)： | 16/24頁(yè) |
| 文件大?。?/td> | 112K |
| 代理商： | PCB2421P |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)當(dāng)前第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)
1997 Apr 01
16
Philips Semiconductors
Preliminary specification
1K dual mode serial EEPROM
PCB2421
11 APPLICATION INFORMATION
11.1
Diode protection
There is no diode connection between VCLK and V
DD
,
SCL and V
DD
and SDA and V
DD
(see Fig.14). This allows
powering-down the device without affecting the I
2
C-bus
operation or loading the VCLK driver.
11.2
Functional compatibility with microchip
24CL21 dual mode EEPROM
The Philips PCB2421 is pin and function compatible with
the 24CL21 providing the following measures are taken in
the application.
1.
Pin 1 (TEST) must be tied to V
DD
2.
Pin 3 (WP) must be tied to V
DD
. This inhibits the write
protection function which does not exist on the 24CL21
at this time
3.
4.
5.
Maximum 100 kHz DDC2B clock frequency
Maximum 25 kHz DDC1 VCLK clock frequency
During EEPROM programming a maximum write time
of 20 ms must be observed
8-byte maximum during page write must be observed
During operation V
DD
must be between 4.5 and 5.5 V
An operating temperature between 0 and +70
°
C must
be observed
Output valid from VCLK (t
VAA
) typical 1
μ
s must be
observed
10. DDC1 mode power-up time (t
VPU
) typical 5
μ
s should
be observed.
6.
7.
8.
9.
Remark
: VCLK is ‘don’t care’ in the DDC2B mode.
Fig.14 PCB2421 diode protection.
handbook, halfpage
MBG284
SCL
SDA
WP
n.c.
VDD
VSS
VCLK
TEST
1
2
3
4
8
7
6
5
substrate
PCB2421
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相關(guān)代理商/技術(shù)參數(shù) |
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|---|---|
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