參數(shù)資料
型號: PCB8517
廠商: NXP Semiconductors N.V.
英文描述: Stand-alone OSD for monitor applications
中文描述: 獨立的監(jiān)視器應用OSD
文件頁數(shù): 6/24頁
文件大?。?/td> 740K
代理商: PCB8517
1997 Mar 03
6
Philips Semiconductors
Objective specification
Stand-alone OSD for monitor applications
PCB8517
D
ATA SEQUENCE AND FORMAT
The PCB8517 provides the following 3 types of
transmission sequence:
Sequence A: R
CA
D
R
CA
D etc.
Sequence B: R
CA
D
CA
D
CA
D etc.
Sequence C: R
CB
D
D
D
D etc.
Where: R = row address,
CA = column address A, CB = column address B,
D = data of RAM.
The column address will be increased by 1 automatically
after each bit of data has been stored into the RAM.
In sequence C, if the column address of the last data is
1FH, the row address will also be increased by 1.
The sequence A is particularly suitable for updating small
amounts of data between different rows. However, if the
current information byte has the same row address as the
previous one, sequence B is recommended. For a greater
information update, such as a power-up situation,
sequence C should be used.
Bit B7 in Table 2 is used to distinguish between row or
column address and bit B6 is used to distinguish between
column address A or B. When A or B sequence is
transmitted, the column address should be formatted as
column address A, and the data format of column
address B is used for sequence C. There are some
limitations on using mixed formats during a single
transmission, for example when pin EN has been pulled to
LOW once.
Allowed:
From A to B or C
From B to A.
Not allowed:
From C to A or B.
Table 2
Data format
Note
1.
X = don’t care.
Internal RAM organization
(see Fig.4)
The internal RAM is addressed with rows 0 to 10 and columns 0 to 31. The OSD character display buffers are located in
columns 0 to 23 of rows 0 to 9. Each display buffer contains a character ROM address and the colour control bit
corresponding to a display location on the monitor screen.
Each row data is associated with two control registers which are located at columns 30 and 31 of their respective row.
Also three window control registers for three windows together with three frame control register occupy the first
13 columns of row 10.
ADDRESS
DATA BYTE
(1)
B7
B6
B5
B4
B3
B2
B1
B0
Row address
Column address A
Column address B
1
0
0
X
0
1
X
X
X
X
C4
C4
R3
C3
C3
R2
C2
C2
R1
C1
C1
R0
C0
C0
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