參數(shù)資料
型號(hào)： PCD50912H
廠商： NXP SEMICONDUCTORS
元件分類： 無(wú)繩電話/電話
英文描述： SHORT ELBOW
中文描述： TELECOM, CORDLESS, BASEBAND CIRCUIT, PQFP80
封裝： 12 X 12 MM, 1.40 MM HEIGHT, PLASTIC, SOT-315-1, LQFP-80
文件頁(yè)數(shù)： 9/16頁(yè)
文件大小： 91K
代理商： PCD50912H
1998 Apr 27
9
Philips Semiconductors
Objective specification
Low cost; low power DECT baseband
controllers (ABC-PRO)
PCD509x2/zuu/v family
Note
1.
In the ‘State After Reset’ column the following symbols are used:
a) HIGH means active HIGH, for BUPxSW pin types this means weak pull-up
b) LOW means active LOW
c) ‘running’ means the clock signal is active
d) ‘off’ means the high-impedance state.
EA
P3.7/RD
P3.6/WR
P3.5/T1
P3.4/T0
P3.3/INT1/IrDA
P3.2/INT0
P3.1/TXD
P3.0/RXD
V
SSD
V
DDD
V
DD(P1,P3)
P1.7/INT9/SDA
P1.6/INT8/SCL
P1.5/INT7/FS1
P1.4/INT6/DCK
P1.3/INT5/DO
P1.2/INT4/DI
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
I
HIGH
HIGH
HIGH
HIGH
HIGH
HIGH
HIGH
HIGH
off
off
HIGH
HIGH
HIGH
HIGH
V
DD(P0,P2)
V
DD(P1,P3)
V
DD(P1,P3)
V
DD(P1,P3)
V
DD(P1,P3)
V
DD(P1,P3)
V
DD(P1,P3)
V
DD(P1,P3)
V
DD(P1,P3)
V
DD(P1,P3)
V
DD(P1,P3)
V
DD(P1,P3)
V
DD(P1,P3)
V
DD(P1,P3)
V
DD(P1,P3)
external access (80C51), active LOW
80C51 port pin/Read data, active LOW
80C51 port pin/Write data, active LOW
80C51 port pin/Timer 1 input
80C51 port pin/Timer 0 input
80C51 port pin/external interrupt 1/IrDA clock
80C51 port pin/external interrupt 0
80C51 port pin/UART transmit data
80C51 port pin/UART receive data
negative supply voltage for digital core
positive supply voltage for digital core
positive supply voltage for periphery pins
80C51 port pin/external interrupt 9/I
2
C-bus data
80C51 port pin/external interrupt 8/I
2
C-bus clock
80C51 port pin/external interrupt 7/SPI Frame Sync
80C51 port pin/external interrupt 6/SPI Data Clock
80C51 port pin/external interrupt 5/SPI Data Out
80C51 port pin/external interrupt 4/SPI Data In
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
SYMBOL
PIN
I/O
STATE
AFTER
RESET
(1)
SUPPLY
DOMAIN
DESCRIPTION
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