參數(shù)資料
型號: PCF51AC256ACFUE
廠商: Freescale Semiconductor
文件頁數(shù): 25/42頁
文件大?。?/td> 0K
描述: MCU 8BIT 256K FLASH 64-QFP
標準包裝: 84
系列: MCF51AC
核心處理器: Coldfire V1
芯體尺寸: 32-位
速度: 50MHz
連通性: CAN,I²C,SCI,SPI
外圍設備: LVD,PWM,WDT
輸入/輸出數(shù): 54
程序存儲器容量: 256KB(256K x 8)
程序存儲器類型: 閃存
RAM 容量: 32K x 8
電壓 - 電源 (Vcc/Vdd): 2.7 V ~ 5.5 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 20x12b
振蕩器型: 外部
工作溫度: -40°C ~ 85°C
封裝/外殼: 64-QFP
包裝: 托盤
Electrical Characteristics
MCF51AC256 ColdFire Microcontroller Data Sheet, Rev.7
Freescale Semiconductor
31
2.9
External Oscillator (XOSC) Characteristics
3 Monotonicity and No-Missing-Codes guaranteed in 10-bit and 8-bit modes
4 Based on input pad leakage current. Refer to pad electricals.
Table 15. Oscillator Electrical Specifications (Temperature Range = –40 to 105
C Ambient)
Num
C
Rating
Symbol
Min
Typical1
1 Data in Typical column was characterized at 5.0 V, 25
C or is typical recommended value.
Max
Unit
1C
Oscillator crystal or resonator (EREFS = 1, ERCLKEN = 1)
Low range (RANGE = 0)
High range (RANGE = 1) FEE or FBE mode2
High range (RANGE = 1) PEE or PBE mode3
High range (RANGE = 1, HGO = 1) BLPE mode
High range (RANGE = 1, HGO = 0) BLPE mode
2 When MCG is configured for FEE or FBE mode, input clock source must be divisible using RDIV to within the range of
31.25 kHz to 39.0625 kHz.
3 When MCG is configured for PEE or PBE mode, input clock source must be divisible using RDIV to within the range of 1 MHz
to 2 MHz.
flo
fhi-fll
fhi-pll
fhi-hgo
fhi-lp
32
1
38.4
5
16
8
kHz
MHz
2
— Load capacitors
C1
C2
See crystal or resonator
manufacturer’s recommendation.
3—
Feedback resistor
Low range (32 kHz to 38.4 kHz)
High range (1 MHz to 16 MHz)
RF
10
1
M
4—
Series resistor
Low range, low gain (RANGE = 0, HGO = 0)
Low range, high gain (RANGE = 0, HGO = 1)
High range, low gain (RANGE = 1, HGO = 0)
High range, high gain (RANGE = 1, HGO = 1)
8 MHz
MHz
RS
0
100
0
0
10
20
k
5T
Crystal start-up time 4
Low range, low gain (RANGE = 0, HGO = 0)
Low range, high gain (RANGE = 0, HGO = 1)
High range, low gain (RANGE = 1, HGO = 0)5
High range, high gain (RANGE = 1, HGO = 1)5
4 This parameter is characterized and not tested on each device. Proper PC board layout procedures must be followed to
achieve specifications.
5 4 MHz crystal
t
CSTL-LP
t
CSTL-HGO
t
CSTH-LP
t
CSTH-HGO
200
400
5
15
ms
6T
Square wave input clock frequency (EREFS = 0, ERCLKEN =
1)
FEE or FBE mode 2
PEE or PBE mode 3
BLPE mode
fextal
0.03125
1
0
5
16
40
MHz
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