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| 型號(hào)： | PCF8890 |
| 英文描述： | 240 + 1 outputs TFT LCD gate driver |
| 中文描述： | 240 1輸出TFT液晶柵極驅(qū)動(dòng)器 |
| 文件頁(yè)數(shù)： | 16/76頁(yè) |
| 文件大?。?/td> | 385K |
| 代理商： | PCF8890 |
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2002 Aug 16
16
Philips Semiconductors
Preliminary specification
STN RGB - 384 output column driver
PCF8832
7.17
DDRAM addressing
Data is written byte-wise into the RAM matrix of the
PCF8832 as illustrated in Fig.11. The display RAM has a
matrix of 168
×
128
×
9 bits. RAM locations are addressed
by the address pointers. The address ranges are
X = 0 to X = 127 (7F) and Y = 0 to Y = 167 (A7H).
Addresses outside of these ranges are not allowed.
Before writing to the RAM, a window must be defined into
which it can be written. The window is programmable via
the command registers with xs and ys designating the
start address, and xe and ye designating the end address.
If, for example, the whole display content is to be written,
the window is defined by the following values: xs = 0 (0H),
ys = 0 (0H), xe = 127 (7FH) and ys = 159 (9FH).
In vertical addressing mode (V = 1), the Y-address
increments after each byte. After the last Y-address
(Y = ye), Y wraps around to ys and X increments to
address the next column. In horizontal addressing mode
(V = 0), the X-address increments after each byte. After
the last X-address (X = xe), X wraps around to xs and
Y increments to address the next row. After the very last
address (X = xe and Y = ye) the address pointers wrap
around to address (X = xs and Y = ys). For flexibility in
handling a wide variety of display architectures, the
commands ‘RAM data addressing’ and ‘data control’
define flags MX, MY and L, which allows mirroring of the
X and Y-addresses and selection of landscape or portrait
mode. All combinations of flags are allowed. The available
combinations of writing to the display RAM are shown in
Figs 12 to 17. When MX, MY, V or L are changed, the
data must be rewritten to the display RAM.
handbook, full pagewidth
MGW668
0
xe
xs
ys
ye
1
2
3
4
5
6
7
167
127
0
Y address
X address
R2 R1 R0 G2 G1 G0 Bi2 Bi1 Bi0
R2 R1 R0 G2 G1 G0 B1 B0
display byte sent via interface
pixel information stored in display RAM
D7
D6
D5
D4
D3
D2
Diii
Dii
Di
R
G
B
Fig.11 RAM format and addressing.
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