參數(shù)資料
型號(hào)： PCI1510GVF
廠商： Texas Instruments, Inc.
英文描述： PC CARD CONTROLLERS
中文描述： PC卡控制器
文件頁數(shù)： 74/128頁
文件大?。?/td> 735K
代理商： PCI1510GVF
414
4.29 System Control Register
System-level initializations are performed by programming this doubleword register. See Table 47 for a complete
description of the register contents.
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Default
0
0
0
0
1
0
0
0
0
1
0
0
0
1
0
0
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Default
1
0
0
1
0
0
0
0
0
1
1
0
0
0
0
0
Register:
Offset:
Type:
Default:
System control
80h
Read-only, Read/Write, Read/Clear
0844 9060h
Table 47. System Control Register Description
BIT
SIGNAL
TYPE
FUNCTION
3130
SER_STEP
RW
Serialized PCI interrupt routing step. Bits 31 and 30 configure the serialized PCI interrupt stream signaling
and accomplish an even distribution of interrupts signaled on the four PCI interrupt slots.
00 = INTA signal in INTA IRQSER slots
01 = INTA signal in INTB IRQSER slots
10 = INTA signal in INTC IRQSER slots
11 = INTA signal in INTD IRQSER slots
2928
RSVD
R
Reserved. Bit 28 returns 0b when read.
Internal oscillator enable.
0 = Internal oscillator is disabled
1 = Internal oscillator is enabled (default)
SMI interrupt routing. Bit 26 selects whether IRQ2 or CSC is signaled when a write occurs to power a PC Card
socket.
0 = PC Card power change interrupts routed to IRQ2 (default)
1 = A CSC interrupt is generated on PC Card power changes
SMI interrupt status. This bit is set when bit 24 (SMIENB) is set and a write occurs to set the socket power.
Writing a 1b to bit 25 clears the status.
0 = SMI interrupt signaled (default)
1 = SMI interrupt not signaled
SMI interrupt mode enable. When bit 24 is set and a write to the socket power control occurs, the SMI interrupt
signaling is enabled and generates an interrupt. This bit defaults to 0b (disabled).
Reserved. Bit 23 returns 0b when read.
CardBus reserved terminals signaling. When a CardBus card is inserted and bit 22 is set, the RSVD CardBus
terminals are driven low. When this bit is 0b, these terminals are placed in a high-impedance state.
0 = Place CardBus RSVD terminals in a high-impedance state
1 = Drive Cardbus RSVD terminals low (default)
VCC protection enable.
0 = VCC protection enabled for 16-bit cards (default)
1 = VCC protection disabled for 16-bit cards
Reduced zoomed video enable. When this bit is enabled, terminals A25A22 of the card interface for PC
Card-16 cards are placed in the high-impedance state. This bit should not be set for normal ZV operation. This
bit is encoded as:
0 = Reduced zoomed video disabled (default)
1 = Reduced zoomed video enabled
27
OSEN
R/W
26
SMIROUTE
RW
25
SMISTATUS
RC
24
SMIENB
RW
23
RSVD
R
22
CBRSVD
RW
21
VCCPROT
RW
20
REDUCEZV
RW
1916
RSVD
RW
Reserved. Do not change the default value.
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