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參數(shù)資料
| 型號： | PCI2050GHK |
| 英文描述： | BUS CONTROLLER |
| 中文描述： | 總線控制器 |
| 文件頁數(shù)： | 9/17頁 |
| 文件大?。?/td> | 220K |
| 代理商： | PCI2050GHK |
PCI2050A
PCI-to-PCI BRIDGE
SCPS067
–
MAY 2001
9
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
Terminal Functions (Continued)
power supply terminals
TERMINAL
DESCRIPTION
NAME
NO.
GND
12, 20, 31, 37, 48, 52, 54,
59, 66, 72, 78, 86, 94, 100,
104, 111, 117, 123, 136,
142, 148, 156, 158, 160,
166, 174, 181, 187, 193,
199, 205
Device ground terminals
VCC
1, 26, 34, 40, 51, 53, 56, 62,
69, 75, 81, 91, 97, 103, 105,
108, 114, 120, 131, 139,
145, 151, 157, 163, 170,
178, 184, 190, 196, 202,
208
Power-supply terminal for core logic (3.3 V)
P_VCCP
124
Primary bus-signaling environment supply. P_VCCP is used in protection circuitry on primary bus
I/O signals.
S_VCCP
135
Secondary bus-signaling environment supply. S_VCCP is used in protection circuitry on secondary
bus I/O signals.
detailed description
The PCI2050 is a bridge between two PCI buses and is compliant with both the PCI local bus specification and
the PCI-to-PCI bridge specification. The bridge supports two 32-bit PCI buses operating at a maximum of 66
MHz. The primary and secondary buses operate independently in either 3.3-V or 5-V signaling environment.
The core logic of the bridge, however, is powered at 3.3 V to reduce power consumption.
Host software interacts with the bridge through internal registers. These registers provide the standard PCI
status and control for both the primary and secondary buses. Many vendor-specific features that exist in the
TI extension register set are included in the bridge. The PCI configuration header of the bridge is only accessible
from the primary PCI interface.
The bridge provides internal arbitration for the nine possible bus masters, and provides each with a dedicated
active low request/grant pair (REQ/GNT). The arbiter features a two-tier rotational scheme with the PCI2050A
bridge defaulting to the highest priority tier. The PCI2050A also supports external arbitration.
Upon system power up, power-on self test (POST) software configures the bridge according to the devices that
exist on subordinate buses, and enables performance-enhancing features of the PCI2050. In a typical system,
this is the only communication with the bridge internal register set.
write combining
PCI2050A supports write combining for upstream and downstream transactions. This feature is used to
combine separate sequential memory write transactions into a single burst transactions. This feature can only
be used if the address of the next memory write transaction is the next sequential address after the address
of the last double word of the previous memory transaction. For example if the current memory transaction ends
at address X and next memory transaction starts at address X+1, then PCI2050A combines both transactions
into a single transaction.
The write combining feature of PCI2050A is enabled by default on power on reset. It can also be disabled by
setting bit 0 of the TI diagnostics register at offset F0h to 1.
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| PCI2050IGHK | 功能描述:外圍驅(qū)動器與原件 - PCI 32B 33 MHz PCI-to- PCI Bridge RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray |
| PCI2050IPDV | 功能描述:外圍驅(qū)動器與原件 - PCI 32B 33 MHz PCI-to- PCI Bridge RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray |
| PCI2050IPDVG4 | 功能描述:外圍驅(qū)動器與原件 - PCI 32B 33 MHz PCI-to- PCI Bridge RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray |
| PCI2050IZHK | 功能描述:外圍驅(qū)動器與原件 - PCI 32B 33 MHz PCI-to- PCI Bridge RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray |
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