參數(shù)資料
型號(hào)： PCI7420GHK
廠商： Texas Instruments
文件頁(yè)數(shù)： 1/7頁(yè)
文件大?。?/td> 0K
描述： IC 2SLT PC CARD/SC CTLR 288-BGA
標(biāo)準(zhǔn)包裝： 90
控制器類型： PC 卡，PCI
接口： 串行 ROM
安裝類型： 表面貼裝
封裝/外殼： 288-LFBGA
供應(yīng)商設(shè)備封裝： 288-BGA Microstar（16x16）
包裝： 托盤
其它名稱： 296-15269
www.ti.com
FEATURES
SLLA252 – JULY 2006
Dual Socket CardBus and Smart Card Controller With Integrated 1394a-2000 OHCI
Two-Port PHY/Link-Layer Controller and Dedicated SD/MS-Pro Sockets
Full IEEE Std 1394a-2000 support includes:
connection debounce, arbitrated short reset,
PC Card Standard 8.0 compliant
multispeed concatenation, arbitration
PCI Bus Power Management Interface
acceleration, fly-by concatenation, and port
Specification 1.1 compliant
disable/suspend/resume
Advanced Configuration and Power Interface
Power-down features to conserve energy in
(ACPI) Specification 2.0 compliant
battery-powered applications include:
PCI Local Bus Specification Revision 2.3
automatic device power down during
compliant
suspend, PCI power management for
PC 98/99 and PC2001 compliant
link-layer, and inactive ports powered down,
Compliant with the PCI Bus Interface
ultralow-power sleep mode
Specification for PCI-to-CardBus Bridges
Two IEEE Std 1394a-2000 fully compliant
Fully compliant with provisions of IEEE Std
cable ports at 100M bits/s, 200M bits/s, and
1394-1995 for a high-performance serial bus
400M bits/s
and IEEE Std 1394a-2000
Cable ports monitor line conditions for active
Fully compliant with 1394 Open Host
connection to remote node
Controller Interface Specification 1.1
Cable power presence monitoring
1.8-V core logic and 3.3-V I/O cells with
Separate cable bias (TPBIAS) for each port
internal voltage regulator to generate 1.8-V
Physical write posting of up to three
core VCC
outstanding transactions
Universal PCI interfaces compatible with
PCI burst transfers and deep FIFOs to
3.3-V and 5-V PCI signaling environments
tolerate large host latency
Supports PC Card or CardBus with hot
External cycle timer control for customized
insertion and removal
synchronization
Supports 132-MBps burst transfers to
Extended resume signaling for compatibility
maximize data throughput on both the PCI
with legacy DV components
bus and the CardBus
PHY-Link logic performs system initialization
Supports serialized IRQ with PCI interrupts
and arbitration functions
Programmable multifunction terminals
PHY-Link encode and decode functions
Serial ROM interface for loading subsystem
included for data-strobe bit level encoding
ID and subsystem vendor ID
PHY-Link incoming data resynchronized to
ExCA-compatible registers are mapped in
local clock
memory or I/O space
Node power class information signaling for
Intel 82365SL–DF register compatible
system power management
Supports ring indicate, SUSPEND, and PCI
Register bits give software control of
CCLKRUN protocol and PCI bus Lock (LOCK)
contender bit, power class bits, link active
Provides VGA/palette memory and I/O, and
control bit, and IEEE Std 1394a-2000 features
subtractive decoding options, LED activity
Isochronous receive dual-buffer mode
terminals
Out-of-order pipelining for asynchronous
Fully interoperable with FireWire and
transmit requests
i.LINK implementations of IEEE Std 1394
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
FireWire is a trademark of Apple Computer, Inc..
i.LINK is a trademark of Sony Corporation of America.
PRODUCTION DATA information is current as of publication date.
Copyright 2006, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
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