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參數(shù)資料
| 型號： | PCI9656-AC66BI |
| 英文描述： | Controller Miscellaneous - Datasheet Reference |
| 中文描述： | 控制器雜項-數(shù)據(jù)表參考 |
| 文件頁數(shù)： | 2/4頁 |
| 文件大?。?/td> | 312K |
| 代理商： | PCI9656-AC66BI |
I
Independent 16 Qword (128 byte) read
and 32 Qword (256 byte) write FIFOs
I
Deferred reads, deferred writes, posted
writes, read ahead, and programmable read
prefetch counter
I
Programmable #READY time out
and recovery
Advanced Performance Features Common to
DMA, Direct Master, and Direct Slave
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Zero wait state PCI & local bus bursts
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Deep FIFOs prolong bursts
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Unaligned PCI and local bus transfers of
any byte length
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On-the-fly Endian conversion
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Programmable local bus wait states
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Parity checking on both buses
Messaging
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Provides industry standard I2O r1.5
messaging unit
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Supports general-purpose messaging
for proprietary message schemes
–
Eight 32-bit mailbox registers for polled
environments
–
Two 32-bit doorbell register for interrupt
driven environments
Embedded Host Features
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PCI arbiter supports 7 external masters
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Reset and interrupt signals configurable for
embedded host operation
I
Type 0/1 Configuration support allows
local bus master to configure PCI bus
and devices
Package
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272-pin PBGA
–
27 mm x 27 mm, 1.27 mm ball pitch
–
Low power 2.5V CMOS core
–
3.3V I/O, 5V tolerant
–
Industrial temperature range operation
–
IEEE 1149.1 JTAG boundary scan
Backward Compatibility
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The PCI 9656 register set is backward
compatible with the PCI 9054, with new
registers added for the new functionality
enhancements
Related PLX Products
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Support for 32-bit, 66MHz PCI with 32-bit,
66MHz C, J, and M Local Bus support is
provided by the PCI 9056
–
See the PCI 9056 product brief for details
Serial EEPROM
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Store configuration register power on,
reset values
I
An alternative to expansion ROM for stor-
ing Vital Product Data (VPD)
I
Supports 2 Kbit/4 Kbit microwire devices
with sequential read
Data Pipe Architecture
DMA
Service DMA descriptors, mastering on both
bus interfaces during data transfer
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Two independent channels provide flexible
prioritization scheme
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Each channel has its own bi-directional
32 Qword (256 byte) deep FIFO
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Block Mode services a single DMA
descriptor in PCI 9656 registers
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Scatter/Gather Mode services DMA
descriptor linked lists in memory
–
Burst descriptors from PCI or local
bus memory
–
Descriptor lists either linear (static) or
circular (dynamic) with Valid bit sema-
phore control
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Direct Hardware DMA controls
–
Demand Mode to pause/resume
–
End of Transfer (EOT) to abort
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Programmable local bus burst length,
including infinite
–
Enhanced M Mode supports bursts beyond
PowerQUICC 16 byte limit
Direct Master
Service local bus masters by mastering on
the PCI bus
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Two local bus address spaces map to PCI
bus: one to memory; one to I/O
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Generate all PCI memory and I/O
transaction types, including Memory
Write and Invalidate (MWI)
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Independent 16 Qword (128 byte) read
and 32 Qword (256 byte) write FIFOs
I
Read ahead and programmable read
prefetch counter
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PowerQUICC deferred reads and IDMA
(M mode only)
Direct Slave
Service PCI bus masters by mastering on the
local bus
I
Two general-purpose and one expansion
ROM PCI address spaces map to local
bus memory
–
Each address space may specify 8-, 16-,
or 32-bit local bus data transfer
PCI 9656 Features
The PCI 9656 64-bit, 66MHz PCI I/O accelera-
tor is the most advanced, general-purpose
bus mastering device available for Motorola
MPC 850/860 PowerQUICC and generic
32-bit, 66MHz local bus based designs. The
PCI 9656 incorporates PLX’s industry leading
Data Pipe Architecture technology, featuring
DMA engines, programmable Direct Master
and Direct Slave data transfer modes, and PCI
messaging functions.
Interfaces
PCI
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64-bit, 66MHz r2.2 operation
–
Zero wait state bursts to 528 MB/s
–
Dual Address Cycle (DAC) support as a
PCI bus master
–
Vital Product Data (VPD)
–
3.3V I/O, 5V tolerant
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PICMG 2.1 r2.0 Hot Swap Silicon
–
Programming Interface 0 (P=0)
–
Bias Voltage Support
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Early Power Support
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Initially Not Responding Support
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PCI Hot Plug r1.0
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PCI Power Management r1.1
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Supports D0, D1, D2, D3
HOT
, & D3
COLD
power states
–
D3
Power Management Event (PME)
generation to meet PC 2001 Windows
98/2000 communication adapter logo
certification requirements
Local Bus
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Three local bus options on the device
–
M Mode: Motorola MPC 850/860
PowerQUICC and PowerPC 80x/82x
–
C Mode: De-multiplexed address and data
buses for Intel i960
, DSPs, custom ASICs
and FPGAs, and others
–
J Mode: Multiplexed address and data
buses for Intel i960, IBM PowerPC 401, IDT
RC32364, DSPs, IOP 480, and others
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32-bit, 66MHz operation
–
Zero wait state bursts to 264 MB/s
–
3.3V I/O, 5V tolerant
–
Asynchronous clock inputs to PCI
and local bus
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| PCI9656-BA66BI | 功能描述:外圍驅(qū)動器與原件 - PCI 64-bit 66MHz PCI Bus Mastering I/O RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray |
| PCI9656-BA66BI G | 制造商:PLX Technology 功能描述:IC PCI BUS MASTER BRIDGE 272PBGA |
| PCI9656-BA66BIG | 制造商:PLX 制造商全稱:PLX 功能描述:64-bit, 66MHz PCI Bus Mastering I/O Accelerator for Motorola PowerQUICC⑩ & Generic 32-bit, 66MHz Local Bus Designs |
| PCI9656-BA66BI-G | 功能描述:外圍驅(qū)動器與原件 - PCI 64-bit 66MHz PCI Bus Mastering I/O RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray |
| PCI9656RDK-LITE | 功能描述:界面開發(fā)工具 PCI9656 KIT RoHS:否 制造商:Bourns 產(chǎn)品:Evaluation Boards 類型:RS-485 工具用于評估:ADM3485E 接口類型:RS-485 工作電源電壓:3.3 V |
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