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參數(shù)資料
| 型號： | PCK2000DL |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | XO, clock |
| 英文描述： | CK97 66/100MHz System Clock Generator |
| 中文描述： | 100 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO48 |
| 封裝： | 7.50 MM, PLASTIC, SSOP-48 |
| 文件頁數(shù)： | 3/14頁 |
| 文件大?。?/td> | 90K |
| 代理商： | PCK2000DL |
Philips Semiconductors
Product specification
PCK2000
CK97 (66/100MHz) System Clock Generator
1998 Sep 29
3
PIN DESCRIPTION
PIN NUMBER
SYMBOL
FUNCTION
1, 2, 47
REF [0–2]
14.318 MHz clock outputs
3
V
SSREF
V
DDREF
XTAL_IN
GROUND for REF outputs
48
POWER for REF outputs
4
14.318 MHz crystal input
5
XTAL_OUT
14.318 MHz crystal output
6, 12, 18
V
SSPCI
[0–2]
PCICLK_F
GROUND for PCI outputs
7
Free-running PCI output
9, 15
V
DDPCI
[0–1]
PCICLK [1–7]
POWER for PCI outputs
8, 10, 11, 13, 14, 16, 17
PCI clock outputs.
19, 33
V
DDCORE
[0–1]
V
SSCORE
[0–1]
V
DD
48MHz
V
SS
48MHz
48MHz [0–1]
Isolated POWER for core
20, 32
Isolated GROUND for core
21
POWER for 48MHz outputs
24
GROUND for 48MHz outputs
22, 23
48MHz outputs
26, 27
SEL0,1
Logic select pins.
25
SEL100/66
Select pin for enabling 66 MHz or 100MHz. L = 66 MHz
H = 100MHz
29
PWRDWN
Control pin to put device in powerdown state, active low
30
CPUSTOP
Control pin to disable CPU clocks, active low
31
PCISTOP
Control pin to disable PCI clocks, active low
37, 41
V
DDCPU
[0–1]
V
SSCPU
[0–1]
CPUCLK [0–3]
POWER for CPU outputs
34, 38
GROUND for CPU outputs
35, 36, 39, 40
CPU clock outputs @2.5V
43
V
SSAPIC
V
DDAPIC
IOAPIC [0–1]
GROUND for IOAPIC outputs
46
POWER for IOAPIC outputs
44, 45
IOAPIC output @ 2.5V
28, 42
RESERVED
Reserved for future use
NOTES:
1. V
DD
and V
SS
names in the above tables reflects a likely internal POWER and GROUND partition to reduce the effects of internal noise on
the performance of the device. In reality, the platform will be configured with the V
DDAPIC
and V
DDCPU
pins tied to a 2.5V supply, all
remaining V
DD
pins tied to a common 3.3V supply and all V
SS
pins being common.
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