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參數(shù)資料
| 型號： | PCK857DGG |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 時鐘及定時 |
| 英文描述： | 66-150MHz Phase Locked Loop Differential 1:10 SDRAM Clock Driver |
| 中文描述： | PLL BASED CLOCK DRIVER, 10 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO48 |
| 封裝： | 6.10 MM, PLASTIC, MO-153, SOT-362-1, TSSOP-48 |
| 文件頁數(shù)： | 2/8頁 |
| 文件大?。?/td> | 62K |
| 代理商： | PCK857DGG |
Philips Semiconductors
Preliminary specification
PCK857
66–150MHz Phase Locked Loop Differential 1:10
SDRAM Clock Driver
2
1998 Dec 10
FEATURES
Optimized for clock distribution in DDR (Double Data Rate)
SDRAM applications
1-to-10 differential clock distribution
Very low skew (
<
100ps) and jitter (
<
100ps)
3V AV
CC
and 2.5V V
ddq
SSTL_2 interface clock inputs and outputs
CMOS control signal input
Test mode enables buffers while disabling PLL
Low current power-down mode
Tolerant of Spread Spectrum input clock
Full DDR solution provided when used with SSTL16857 and
CBT3857
DESCRIPTION
Zero delay buffer to distribute an SSTL differential clock input pair to
10 SSTL_2 differential output pairs. Outputs are slope controlled.
External feedback pin for synchronization of the outputs to the input.
A CMOS style Enable/Disable pin is provided for low power disable.
PIN CONFIGURATION
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
21
22
23
24
41
42
43
44
45
46
47
48
GND
Y
0
Y
0
V
DDQ
Y
1
Y
1
GND
Y
2
Y
2
GND
V
DDQ
V
DDQ
CLK
CLK
V
DDQ
AV
CC
AGND
GND
Y
3
Y
3
V
DDQ
Y
4
Y
4
GND
GND
Y
5
Y
5
V
DDQ
Y
6
Y
6
GND
GND
Y
7
Y
7
V
DDQ
G
FBIN
FBIN
V
DDQ
FBOUT
FBOUT
GND
Y
8
Y
8
V
DDQ
Y
9
Y
9
GND
SW00358
ORDERING INFORMATION
PACKAGES
48-Pin Plastic TSSOP
TEMPERATURE RANGE
0
°
C to +70
°
C
OUTSIDE NORTH AMERICA
PCK857 DGG
NORTH AMERICA
PCK857 DGG
DRAWING NUMBER
SOT362-1
PINS
SYMBOL
GND
DESCRIPTION
SSTL_2 ground pins
1, 7, 8, 18, 24, 25, 31, 41, 42, 48
2, 3, 5, 6, 9, 10, 19, 20, 22, 23, 26, 27, 29,
30, 32, 33, 39, 40, 43, 44, 46, 47
4, 11, 12, 15, 21, 28, 34
13, 14, 35, 36
16
17
37
Y
n
, Y
nb
, FB
OUT
, FB
OUTb
SSTL_2 differential outputs
V
DDQ
SSTL_2 power pins
SSTL_2 differential inputs
Analog power
Analog ground
Power-down control input
CLK
IN
, CLK
INb
, FB
IN
, FB
INb
AV
CC
AGND
G
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| PCK857DGG,512 | 功能描述:鎖相環(huán) - PLL 1:10 SDRAM CLK INPUTS RoHS:否 制造商:Silicon Labs 類型:PLL Clock Multiplier 電路數(shù)量:1 最大輸入頻率:710 MHz 最小輸入頻率:0.002 MHz 輸出頻率范圍:0.002 MHz to 808 MHz 電源電壓-最大:3.63 V 電源電壓-最小:1.71 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:QFN-36 封裝:Tray |
| PCK857DGG,518 | 功能描述:鎖相環(huán) - PLL 1:10 SDRAM CLK INPUTS RoHS:否 制造商:Silicon Labs 類型:PLL Clock Multiplier 電路數(shù)量:1 最大輸入頻率:710 MHz 最小輸入頻率:0.002 MHz 輸出頻率范圍:0.002 MHz to 808 MHz 電源電壓-最大:3.63 V 電源電壓-最小:1.71 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:QFN-36 封裝:Tray |
| PCK857DG-T | 功能描述:鎖相環(huán) - PLL 1:10 SDRAM CLK NPUTS RoHS:否 制造商:Silicon Labs 類型:PLL Clock Multiplier 電路數(shù)量:1 最大輸入頻率:710 MHz 最小輸入頻率:0.002 MHz 輸出頻率范圍:0.002 MHz to 808 MHz 電源電壓-最大:3.63 V 電源電壓-最小:1.71 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:QFN-36 封裝:Tray |
| PCK940L | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Low voltage 1 : 18 clock distribution chip |
| PCK940LBD | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Low voltage 1 : 18 clock distribution chip |
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