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參數(shù)資料
| 型號： | PCM1601 |
| 英文描述： | 24-Bit, 96kHz Sampling, 6-Channel, Enhanced Multi-Level, Delta-Sigma DIGITAL-TO-ANALOG CONVERTER |
| 中文描述： | 24位，96kHz采樣，6通道，增強的多級，Δ-Σ數(shù)字模擬轉(zhuǎn)換器 |
| 文件頁數(shù)： | 19/28頁 |
| 文件大?。?/td> | 253K |
| 代理商： | PCM1601 |
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19
PCM1600, PCM1601
B15
B14
B13
B12
B11
B10
B9
B8
B7
B6
B5
B4
B3
B2
B1
B0
REGISTER 9
R/W
IDX6
IDX5
IDX4
IDX3
IDX2
IDX1
IDX0
res
res
FLT0
CLKD
CLKE
FMT2
FMT1
FMT0
R/W
Read/Write Mode Select
When R/W = 0, a Write operation is performed.
When R/W = 1, a Read operation is performed.
Default Value: 0
FLT0
Digital Filter Roll-Off Control
These bits are Read/Write.
Default Value: 000
B
FLT0 = 0
FLT0 = 1
Sharp Roll-Off (default)
Slow Roll-Off
Bit FLT0 allows the user to select the digital filter roll-off that is best suited to their application. Two filter roll-
off sections are available: Sharp or Slow. The filter responses for these selections are shown in the Typical
Performance Curves section of this data sheet.
CLKD
SCLKO Frequency Selection
This bit is Read/Write.
Default Value: 0
CLKD = 0
CLKD = 1
Full Rate, f
SCLKO
= f
SCLKI
(default)
Half Rate, f
SCLKO
= f
SCLKL
/2
The CLKD bit is used to determine the clock frequency at the system clock output pin, SCLKO.
CLKE
SCLKO Output Enable
This bit is Read/Write.
Default Value: 0
CLKE = 0
CLKE = 1
SCLKO Enabled (default)
SCLKO Disabled
The CLKE bit is used to enable or disable the system clock output pin, SCLKO. When SCLKO is enabled, it
will output either a full or half rate clock, based upon the setting of the CLKD bit. When SCLKO is disabled,
it is set to a high impedance state.
FMT[2:0]
Audio Interface Data Format
These bits are Read/Write.
Default Value: 000
B
FMT[2:0]
Audio Data Format Selection
000
001
010
011
100
101
110
111
24-Bit Standard Format, Right-Justified Data (default)
20-Bit Standard Format, Right-Justified Data
18-Bit Standard Format, Right-Justified Data
16-Bit Standard Format, Right-Justified Data
I
2
S Format, 16- to 24-bits
Left-Justified Format, 16- to 24-Bits
Reserved
Reserved
The FMT[2:0] bits are used to select the data format for the serial audio interface.
相關PDF資料 |
PDF描述 |
|---|---|
| PCM1600Y | 24-Bit, 96kHz Sampling, 6-Channel, Enhanced Multi-Level, Delta-Sigma DIGITAL-TO-ANALOG CONVERTER |
| PCM1601Y | 24-Bit, 96kHz Sampling, 6-Channel, Enhanced Multi-Level, Delta-Sigma DIGITAL-TO-ANALOG CONVERTER |
| PCM1700U-K | Dual 18-Bit Monolithic Audio DIGITAL-TO-ANALOG CONVERTER |
| PCM1700U-J | Dual 18-Bit Monolithic Audio DIGITAL-TO-ANALOG CONVERTER |
| PCM1700 | Dual 18-Bit Monolithic Audio DIGITAL-TO-ANALOG CONVERTER |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| PCM1601Y | 功能描述:IC 24BIT 96KHZ 6-CHAN D/A 48MQFP RoHS:否 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 數(shù)模轉(zhuǎn)換器 系列:SoundPlus™ 產(chǎn)品培訓模塊:Data Converter Basics 標準包裝:250 系列:- 設置時間:- 位數(shù):24 數(shù)據(jù)接口:串行 轉(zhuǎn)換器數(shù)目:6 電壓電源:模擬和數(shù)字 功率耗散（最大）:240mW 工作溫度:-25°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:48-LQFP 供應商設備封裝:48-LQFP（7x7） 包裝:托盤 輸出數(shù)目和類型:6 電壓，單極 采樣率（每秒）:192k 產(chǎn)品目錄頁面:902 (CN2011-ZH PDF) 配用:DEM-DAI1602-ND - EVAL FIXTURE FOR PCM1602 其它名稱:296-9642296-9642-5296-9642-5-ND296-9642-ND |
| PCM1601Y/1K | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:D/A CONVERTER |
| PCM1602 | 制造商:TI 制造商全稱:Texas Instruments 功能描述:24-Bit, 192kHz Sampling, 6-Channel, Enhanced Multilevel, Delta-Sigma DIGITAL-TO-ANALOG CONVERTER |
| PCM1602 CL001 | 制造商:Alpha Wire Company 功能描述:CBL 2COND 16AWG CLR 1000' |
| PCM1602 CL005 | 制造商:Alpha Wire Company 功能描述:CBL 2COND 16AWG CLR 100' |
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