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參數(shù)資料
| 型號： | PCM1794ADBRG4 |
| 英文描述： | 24-bit,192-khz sampling,advanced segment, audio stereo digital-to-analog converter |
| 中文描述： | 24位,192 - kHz的采樣，先進的部分，立體聲音頻數(shù)字模擬轉換器 |
| 文件頁數(shù)： | 13/30頁 |
| 文件大小： | 301K |
| 代理商： | PCM1794ADBRG4 |
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SLES117A – AUGUST 2004 – REVISED NOVEMBER 2006
www.ti.com
13
SYSTEM CLOCK AND RESET FUNCTIONS
System Clock Input
The PCM1794A requires a system clock for operating the digital interpolation filters and advanced segment DAC
modulators. The system clock is applied at the SCK input (pin 7). The PCM1794A has a system clock detection circuit
that automatically senses the frequency at which the system clock is operating. Table 1 shows examples of system
clock frequencies for common audio sampling rates.
Figure 18 shows the timing requirements for the system clock input. For optimal performance, it is important to use
a clock source with low phase jitter and noise. One of the Texas Instruments PLL1700 family of multiclock generators
is an excellent choice for providing the PCM1794A system clock.
Table 1. System Clock Rates for Common Audio Sampling Frequencies
SAMPLING FREQUENCY
SYSTEM CLOCK FREQUENCY (fSCK) (MHz)
256 fS
8.192
128 fS
4.096
192 fS
6.144
384 fS
12.288
512 fS
16.384
768 fS
24.576
32 kHz
44.1 kHz
5.6488
8.4672
11.2896
16.9344
22.5792
33.8688
48 kHz
6.144
9.216
12.288
18.432
24.576
36.864
96 kHz
12.288
18.432
24.576
36.864
49.152
(1)
73.728
(1)
192 kHz
24.576
36.864
49.152
73.728
(1)This system clock rate is not supported for the given sampling frequency.
t(SCKH)
t(SCY)
System Clock (SCK)
t(SCKL)
2 V
0.8 V
H
L
PARAMETERS
MIN
MAX
UNITS
t(SCY)
t(SCKH)
t(SCKL)
System clock pulse cycle time
13
ns
System clock pulse duration, HIGH
0.4 (SCY)
0.4 (SCY)
ns
System clock pulse duration, LOW
ns
Figure 18. System Clock Input Timing
Power-On and External Reset Functions
The PCM1794A includes a power-on reset function. Figure 19 shows the operation of this function. With V
DD
> 2
V, the power-on reset function is enabled. The initialization sequence requires 1024 system clocks from the time
V
DD
> 2 V.
The PCM1794A also includes an external reset capability using the RST input (pin 14). This allows an external
controller or master reset circuit to force the PCM1794A to initialize to its default reset state.
Figure 20 shows the external reset operation and timing. The RST pin is set to logic 0 for a minimum of 20 ns. The
RST pin is then set to a logic 1 state, thus starting the initialization sequence, which requires 1024 system clock
periods. The external reset is especially useful in applications where there is a delay between the PCM1794A power
up and system clock activation.
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| PCM1794AQDBRQ1 | 功能描述:DAC, Audio 24 bit 192k I2S, PCM 28-SSOP 制造商:texas instruments 系列:- 包裝:剪切帶（CT） 零件狀態(tài):有效 類型:DAC，音頻 分辨率（位）:24 b 采樣率（每秒）:192k 數(shù)據(jù)接口:I2S，PCM 電壓源:模擬和數(shù)字 電壓 - 電源:3 V ~ 3.6 V，5V 工作溫度:-25°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:28-SSOP（0.209"，5.30mm 寬） 供應商器件封裝:28-SSOP 標準包裝:1 |
| PCM1794DB | 功能描述:音頻數(shù)/模轉換器 IC 24-Bit 192kHz Smplng Adv Stg Stereo DAC RoHS:否 制造商:Texas Instruments 轉換器數(shù)量: 分辨率:16 bit 接口類型:I2S, UBS 轉換速率: 信噪比:98 dB 工作電源電壓:5 V DAC 輸出端數(shù)量:2 工作溫度范圍:- 25 C to + 85 C 電源電流:23 mA 安裝風格:SMD/SMT 封裝 / 箱體:TQFP-32 封裝:Reel |
| PCM1794DB | 制造商:Texas Instruments 功能描述:24BIT AUDIO DAC SMD 1794 SSOP28 |
| PCM1794DBG4 | 功能描述:音頻數(shù)/模轉換器 IC 24-Bit 192kHz Smplng Adv Stg Stereo DAC RoHS:否 制造商:Texas Instruments 轉換器數(shù)量: 分辨率:16 bit 接口類型:I2S, UBS 轉換速率: 信噪比:98 dB 工作電源電壓:5 V DAC 輸出端數(shù)量:2 工作溫度范圍:- 25 C to + 85 C 電源電流:23 mA 安裝風格:SMD/SMT 封裝 / 箱體:TQFP-32 封裝:Reel |
| PCM1794DBR | 功能描述:音頻數(shù)/模轉換器 IC 24-Bit 192kHz Smplng Adv Stg Stereo DAC RoHS:否 制造商:Texas Instruments 轉換器數(shù)量: 分辨率:16 bit 接口類型:I2S, UBS 轉換速率: 信噪比:98 dB 工作電源電壓:5 V DAC 輸出端數(shù)量:2 工作溫度范圍:- 25 C to + 85 C 電源電流:23 mA 安裝風格:SMD/SMT 封裝 / 箱體:TQFP-32 封裝:Reel |
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