參數(shù)資料
型號(hào): PCM1796
元件分類: DAC
英文描述: 24BIT 192 KHZ SAMPLING ADVANCED SEGMENT AUDIO STEREO DIGITAL TO ANALOG CONVERTER
中文描述: 24位192千赫采樣高級(jí)分段音頻立體聲數(shù)模轉(zhuǎn)換器
文件頁數(shù): 42/57頁
文件大?。?/td> 512K
代理商: PCM1796
SLES100 DECEMBER 2003
www.ti.com
42
Requirements for System Clock
For operation in the DSD mode, the bit clock (DBCK) is required on pin 7 of the PCM1796. The frequency of the bit
clock can be N times the sampling frequency. Generally, N is 64 in DSD applications.
The interface timing between the bit clock and DSDL and DSDR is required to meet the setup and hold time
specifications shown in Figure 44.
t = 1/(64
×
44.1 kHz)
D1
DSDL
DSDR
D0
D2
D3
D4
DBCK
Figure 43. Normal Data Output Form From DSD Decoder
DSDL
DSDR
t(BCH)
DBCK
t(BCL)
t(BCY)
1.4 V
1.4 V
t(DS)
t(DH)
PARAMETER
DBCK pulse cycle time
MIN
85(1)
MAX
UNITS
ns
t(BCY)
t(BCH)
t(BCL)
t(DS)
t(DH)
(1)2.8224 MHz
×
4. (2.8224 MHz = 64
×
44.1 kHz. This value is
specified as a sampling rate of DSD.)
DBCK high-level time
30
ns
DBCK low-level time
30
ns
DSDL, DSDR setup time
10
ns
DSDL, DSDR hold time
10
ns
Figure 44. Timing for DSD Audio Interface
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