參數(shù)資料
型號: PCM3168ATPAPQ1
廠商: Texas Instruments
文件頁數(shù): 19/68頁
文件大?。?/td> 0K
描述: IC 24-BIT AUDIO CODEC 64-HTQFP
標(biāo)準(zhǔn)包裝: 160
類型: 音頻編解碼器
數(shù)據(jù)接口: 串行
分辨率(位): 24 b
ADC / DAC 數(shù)量: 6 / 8
三角積分調(diào)變:
S/N 比,標(biāo)準(zhǔn) ADC / DAC (db): 107 / 112(差分),104 / 112(單端)
動態(tài)范圍,標(biāo)準(zhǔn) ADC / DAC (db): 107 / 112(差分),104 / 112(單端)
電壓 - 電源,模擬: 4.5 V ~ 5.5 V
電壓 - 電源,數(shù)字: 3 V ~ 3.6 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 64-TQFP 裸露焊盤
供應(yīng)商設(shè)備封裝: 64-HTQFP(10x10)
包裝: 托盤
產(chǎn)品目錄頁面: 1077 (CN2011-ZH PDF)
其它名稱: 296-23900-5
LRCKDA
(Slave)
BCKDA
Left-JustifiedMode
DIN1
(Dual)
I SMode
2
DIN1
(Dual)
Left-JustifiedMode
DIN1/2
(Quad)
I SMode
2
DIN1/2
(Quad)
1/f (256BCKsatDualRate,128BCKsatQuadRate)
S
23 22
0
23 22
0
23 22
0
23 22
0
23 22
0
23 22
0
23 22
0
23 22
0
23 22
1
0
23 22
1 0
23 22
1 0
23 22
1 0
23 22
0
23 22
0
23 22
0
23 22
0
23 22
0
23 22
0
23 22
0
23 22
0
23 22
1
0
1
0
1
0
23 22
1
0
23 22
Ch1
32BCKs
Ch2
32BCKs
Ch3
32BCKs
Ch4
32BCKs
Ch5
32BCKs
Ch6
32BCKs
Ch7
32BCKs
Ch8
32BCKs
Ch1/Ch5
32BCKs
Ch2/Ch6
32BCKs
Ch3/Ch7
32BCKs
Ch4/Ch8
32BCKs
AUDIO INTERFACE TIMING
BCKAD/DA
(Input)
1.4V
0.5
VDD
t
LRS
t
DOD
LRCKAD/DA
(Input)
DOUT1/2/3
DIN1/2/3/4
t
DIH
t
LRH
t
DIS
t
BCH
t
BCL
t
BCY
SBAS452 – SEPTEMBER 2008 ......................................................................................................................................................................................... www.ti.com
Figure 41. Audio Data Format: 24-Bit High-Speed TDM Format
(SCKI = 128 fS, 256 fS, DAC, and Slave Mode Only)
Figure 42 through Figure 45 describe the detailed interface timing specifications.
Figure 42. Audio Interface Timing Requirements for Left-Justified, Right-Justified, and I2S Data Formats
(Slave Mode)
Table 9. Timing Requirements for Figure 42(1)
SYMBOL
DESCRIPTION
MIN
TYP
MAX
UNIT
tBCY
BCKAD/DA cycle time
75
ns
tBCH
BCKAD/DA pulse width high
35
ns
tBCL
BCKAD/DA pulse width low
35
ns
tLRS
LRCKAD/DA setup time to BCKAD/DA rising edge
10
ns
tLRH
LRCKAD/DA hold time to BCKAD/DA rising edge
10
ns
tDIS
DIN1/2/3/4 setup time to BCKDA rising edge
10
ns
tDIH
DIN1/2/3/4 hold time to BCKDA rising edge
10
ns
tDOD
DOUT1/2/3 delay time from BCKAD falling edge
0
30
ns
(1)
Load capacitance of output is 20 pF.
26
Copyright 2008, Texas Instruments Incorporated
Product Folder Link(s): PCM3168A PCM3168A-Q1
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