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參數(shù)資料
| 型號： | PCM3793ARHBTG4 |
| 元件分類： | Codec |
| 英文描述： | 16-Bit, Low-Power Stereo Audio CODEC With Microphone Bias, Headphone, and Digital Speaker Amplifier |
| 中文描述： | 16位，低功耗立體聲音頻編解碼器麥克風(fēng)偏置，耳機，揚聲器放大器和數(shù)字 |
| 文件頁數(shù)： | 20/68頁 |
| 文件大小： | 982K |
| 代理商： | PCM3793ARHBTG4 |
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DESCRIPTION OF OPERATION
System Clock Input
t
w(SCKH)
SCKI
t
w(SCKL)
0.7 V
IO
0.3 V
IO
T0005-12
Power-On Reset and System Reset
Power On/Off Sequence
PCM3793A
PCM3794A
SLAS529A–JANUARY 2007–REVISED FEBRUARY 2007
The PCM3793A/94A can accept clocks of various frequencies without a PLL. They are used for clocking the
digital filters and automatic level control and delta-sigma modulators and are classified as common-audio and
application-specific clocks.
Table 2
shows frequencies of the common-audio clock and application-specific clock.
Figure 26
shows the timing requirements for system clock inputs. The sampling rate and frequency of the
system clocks are determined by the settings of register 86 (MSR[2:0]) and register 85 (NPR[5:0]). Note that the
sampling rate of the application-specific clock has a little sampling error. The details are shown in
Table 12
.
Table 2. System Clock Frequencies
CLOCK
FREQUENCIES
Common-audio clock
Application-specific clock
11.2896, 12.288, 16.9344, 18.432 MHz
12, 13, 13.5, 24, 26, 27, 19.2, 19.68, 38.4, 39.36 MHz
PARAMETERS
SYMBOL
t
w(SCKH)
t
w(SCKL)
MIN
7
7
UNITS
ns
ns
System-clock pulse duration, high
System-clock pulse duration, low
Figure 26. System Clock Timing
The power-on-reset circuit outputs a reset signal, typically at V
DD
= 1.2 V, and this circuit does not depend on
the voltage of other power supplies (V
CC
, V
PA
, and V
IO
). Internal circuits are cleared to default status, then
signals are removed from all analog and digital outputs. The PCM3793A/94A does not require any power supply
sequencing. Register data must be written after turning all power supplies on.
System reset is enabled by setting register 85 (SRST = 1). After the reset sequence, the register data is reset to
SRST = 0 automatically. All circuits are cleared to their default status at once by the system reset. Note that the
PCM3793A/94A has audible pop noise on the analog outputs when enabling SRST.
To reduce audible pop noise, a sequence of register settings is required after turning all power supplies on when
powering up, or before turning the power supplies off when powering down. If some modules are not required for
a particular application or operation, they should be placed in the power-down state after performing the
power-on sequence. The recommended power-on and power-off sequences are shown in
Table 3
and
Table 4
,
respectively.
20
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| PCM3793RHB | 制造商:BB 制造商全稱:BB 功能描述:16-Bit, Low-Power Stereo Audio CODEC With Microphone Bias, Headphone, and Digital Speaker Amplifier |
| PCM3793RHBR | 功能描述:接口—CODEC Very Lo-Pwr Stereo CODEC RoHS:否 制造商:Texas Instruments 類型: 分辨率: 轉(zhuǎn)換速率:48 kSPs 接口類型:I2C ADC 數(shù)量:2 DAC 數(shù)量:4 工作電源電壓:1.8 V, 2.1 V, 2.3 V to 5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:DSBGA-81 封裝:Reel |
| PCM3793RHBRG4 | 功能描述:接口—CODEC Very Lo-Pwr Stereo CODEC RoHS:否 制造商:Texas Instruments 類型: 分辨率: 轉(zhuǎn)換速率:48 kSPs 接口類型:I2C ADC 數(shù)量:2 DAC 數(shù)量:4 工作電源電壓:1.8 V, 2.1 V, 2.3 V to 5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:DSBGA-81 封裝:Reel |
| PCM3793RHBT | 功能描述:接口—CODEC Very Lo-Pwr Stereo CODEC RoHS:否 制造商:Texas Instruments 類型: 分辨率: 轉(zhuǎn)換速率:48 kSPs 接口類型:I2C ADC 數(shù)量:2 DAC 數(shù)量:4 工作電源電壓:1.8 V, 2.1 V, 2.3 V to 5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:DSBGA-81 封裝:Reel |
| PCM3793RHBTG4 | 功能描述:接口—CODEC Very Lo-Pwr Stereo CODEC RoHS:否 制造商:Texas Instruments 類型: 分辨率: 轉(zhuǎn)換速率:48 kSPs 接口類型:I2C ADC 數(shù)量:2 DAC 數(shù)量:4 工作電源電壓:1.8 V, 2.1 V, 2.3 V to 5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:DSBGA-81 封裝:Reel |
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