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參數(shù)資料
| 型號： | PCM4201 |
| 英文描述： | Low Power, 24-Bit, Single Channel Audio Analog-to-Digital Converter |
| 中文描述： | 低功耗，24位，單聲道音頻模擬數(shù)字轉(zhuǎn)換器 |
| 文件頁數(shù)： | 13/21頁 |
| 文件大?。?/td> | 248K |
| 代理商： | PCM4201 |
SBAS342A DECEMBER 2004 REVISED MARCH 2005
www.ti.com
13
Slave mode operation requires that the FSYNC and BCK
clocks be generated from an external audio processor or
master timing generator, as shown in Figure 5. Both clocks
are inputs in Slave mode. The FSYNC clock rate is the
equal to the desired output sampling frequency, f
S
. The
FSYNC high pulse width must be equal to at least one BCK
clock period. The BCK clock rate should be 128f
S
for
Normal Speed modes (both Low Power and High
Performance), while the BCK clock rate is 64f
S
for Double
Speed mode.
FSR
CLKR
DR
FSYNC
SCKI
BCK
DATA
PCM4201
AUDIO DSP
System
Clock
S/M
V
DD
Figure 5. PCM4201 Slave Mode Configuration
For Master mode operation, the PCM4201 generates the
FSYNC and BCK clocks, deriving them from the system
clock input, SCKI (pin 12), as shown in Figure 6. The
FSYNC clock rate is equal to the output sampling
frequency, f
S
. The FSYNC clock duty cycle is 50% in
Master mode. The BCK clock rate is fixed at 128f
S
for
Normal Speed modes (both Low Power and High
Performance), and 64f
S
for Double Speed mode.
FSR
CLKR
DR
FSYNC
SCKI
BCK
DATA
PCM4201
AUDIO DSP
System
Clock
S/M
DGND
Figure 6. PCM4201 Master Mode Configuration
DIGITAL HIGH-PASS FILTER
The PCM4201 includes a digital high-pass filter, which is
located at the output of the digital decimation filter block.
The purpose of the high-pass filter is to remove the DC
component from the digitized signal. The corner, or 3dB
frequency, for the digital high-pass filter is calculated using
the following relationship:
f
3dB
f
S
48000
where f
S
= the output sampling frequency.
The digital high-pass filter may be enabled or disabled
using the HPFD input (pin 8). When HPFD is forced low,
the high-pass filter is enabled. Forcing HPFD high
disables the high-pass filter. Distortion for signal
frequencies less than 100Hz may increase slightly when
the high-pass filter is enabled.
RESET OPERATION
The PCM4201 includes two reset functions: power on and
externally controlled. This section describes the operation
of each of these functions.
On power up, the internal reset signal is forced low, forcing
the PCM4201 into a reset state. The power-on reset circuit
monitors the V
DD
(pin 13) and V
CC
(pin 4) power supplies.
When the digital supply exceeds 0.6
×
V
DD
nominal
±
400mV, and the V
CC
supply exceeds +4.0V
±
400mV, the
internal reset signal is forced high. The PCM4201 will then
wait for the system clock input (SCKI) to become active.
Once the system clock has been detected, the initialization
sequence begins. The initialization sequence requires
1024 system clock periods for completion. During the
initialization sequence, the ADC output data pin will be
forced low. Once the initialization sequence is completed,
the PCM4201 outputs valid data. Figure 7 shows the
power-on reset sequence timing.
The user may force a reset initialization sequence at any
time while the system clock input is active by utilizing the
RST input (pin 7). The RST input is active low, and requires
a minimum low pulse width of 40ns. The low-to-high
transition of the applied reset signal will force an
initialization sequence to begin. As in the case of the
power-on reset, the initialization sequence requires 1024
system clock periods for completion. Figure 8 illustrates
the reset sequence initiated when using the RST input.
Figure 9 shows the state of the audio data output (DATA)
for the PCM4201 before, during, and after the reset
operations.
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