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參數(shù)資料
| 型號： | PDSP16116AMCAC1R |
| 廠商： | ZARLINK SEMICONDUCTOR INC |
| 元件分類： | 數(shù)字信號處理外設(shè) |
| 英文描述： | 16 by 16 Bit Complex Multiplier |
| 中文描述： | 16-BIT, DSP-MULTIPLIER, CPGA144 |
| 封裝： | POWER, PGA-144 |
| 文件頁數(shù)： | 15/18頁 |
| 文件大?。?/td> | 157K |
| 代理商： | PDSP16116AMCAC1R |
PDSP16116/A/MC
15
As FFT data consists of real and imaginary parts, either
two PDSP1601As must be used (controlled by the same logic)
or a single PDSP1601/A could be used handling real and
imaginary data on alternate cycles (using the same
instructions for both cycles).
An example of an output normalisation circuit is shown in
Fig.8. Only 4 bit data paths are used in calculating the shift.
This means that we must be able to trap very small values
negative of GWR and force a 15-bit right shift in such cases.
N.B.
It is easier to simply add the word tag to the exponent for
the purpose of determing the shift required, instead of
modifying it according to Table.6. To compensate for this, the
Universal Exponent may be increased by one.
SV-PORT
B-PORT
IS
C-PORT
sign bit
4-BIT ADDER
4-BIT SUBTRACTOR
4-BIT MUX
1111
UNVERSAL
EXPONENT
WTOUT
GWR
16-BIT DATA
NORMALISED OUTPUT DATA
ASRSV
PDSP1601
Fig.9 Output Normalisation Circuitry
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| PDSP16116AMCGC1R | 16 by 16 Bit Complex Multiplier |
| PDSP16116MC | 16 by 16 Bit Complex Multiplier |
| PDSP16116MCAC1R | 16 by 16 Bit Complex Multiplier |
| PDSP16116MCGC1R | 16 by 16 Bit Complex Multiplier |
| PDSP16510 | 16 by 16 Bit Complex Multiplier |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| PDSP16116AMCGC1R | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:16 by 16 Bit Complex Multiplier |
| PDSP16116AMCGGDR | 制造商:MITEL 制造商全稱:Mitel Networks Corporation 功能描述:16 X 16 Bit Complex Multiplier |
| PDSP16116B0/AC | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Multiplier |
| PDSP16116BB0AC | 制造商:MITEL 制造商全稱:Mitel Networks Corporation 功能描述:16 X 16 Bit Complex Multiplier |
| PDSP16116C0AC | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Multiplier |
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