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參數(shù)資料
| 型號： | PDSP16340 |
| 廠商： | Zarlink Semiconductor Inc. |
| 英文描述： | 32K BUCKET BUFFER |
| 中文描述： | 32K的鏟斗緩沖區(qū) |
| 文件頁數(shù)： | 7/11頁 |
| 文件大?。?/td> | 302K |
| 代理商： | PDSP16340 |
PDSP16540
5
Characteristic
Min
Max
Notes
RS Period,Tp
RS Low Time
RS High Time
WS Period
WS Period
25ns
8ns
8ns
2Tp+10ns
Tp x L
N
Both conditions must be satisfied
L = Block length, N = amount of new data written
WS Low Time
WS High Time
WEN
set up wrt WS going high
WEN
Hold wrt WS going high
Data In Set Up wrt RS going high
Data In Hold Time wrt RS going high
Delay from RS going high to O/P Data
DAV
,RMF transition wrt to RS going high 10ns
Time to go Low Z wrt to RS going high
Time to go High Z wrt to RS going high
10ns
10ns
2 ns
8 ns
8 ns
0 ns
WEN
going active or in-active
19ns
18ns
19ns
12ns
All output delays are with 30pf loads
Going active or in-active
Occurs when DAV also goes active
Occurs when DAV also goes in-active
NS > 1024B + 1024BS + T + D
S-B
where N is the amount of new data written to the buffer, S is
the period of the write strobe, B is the read strobe period, T is
the transform time as given in the data sheet for the
PDSP16510, and D is the time to transfer data from the
PDSP16510 to the next system device.
It must be noted that the above minimum write period only
applies if continuous inputs are to transformed without the loss
of any incoming information. Peak writing rates can be much
higher if gaps occur within the incoming data stream. The
minimum periods given in Table 1 then limit the writing rate.
When the PDSP16510 uses a 40 MHz clock, dumps its
transformed data with a 40MHz strobe, and the PDSP16540
uses a 40 MHz read strobe, then the minimum S period is149
ns. This equates to a 6.7 MHz writing rate when blocks are not
overlapped, 3.35 MHz with 50% overlaps ( 512 new words), or
1.675MHz with 75% overlaps ( 256 new words).
Figure 2 shows a 1024 point system which allows the
amount of overlap to be any value within 32 words. The 5 bit
overlap code defines groups of 32 new words which are
written to the buffer, in addition to the minimum number of 32
words. The smaller the number of new words written, the
greater is the overlap with the previous block.
During reset the D31:0 outputs from the PDSP16540 will
be high impedance and the 5 bit code is inputed on D9:5. This
high impedance state also allows the PDSP16510 control
parameters to be inputed on its AUX 15:0 bus without any
conflicts.
The rate at which data is written to the PDSP16540 must
be such that 1024 words can be transferred between the
devices, transformed , and then moved to the output circuit for
analysis before the DAV flag goes active again. Since the read
operation is interrupted for one cycle every time a write
operation occurs, the equation controlling the minimum writ-
ing period is given by;
Table 1. Timing Information
D
I
R
PDSP16510
D
I
S
AUX
D
D
D
PDSP16540
BUCKET
BUFFER
D
GND
WS
RS
REAL
IMAG'
DAV
SYSTEM
CLOCK
WEN
MD5:0
GND
510 PARAMETERS
SAMPLE CLOCK
POWER ON RESET
RES
GND
D
I
R
PDSP16510
D
I
S
AUX
D
D
D
PDSP16540
BUCKET
BUFFER
D
GND
WS
RS
REAL
IMAG'
DAV
SYSTEM
CLOCK
WEN
MD5
GND
510 PARAMETERS
SAMPLE CLOCK
POWER ON RESET
RES
GND
IP
15:0
IP
31:16
D
31:16
D
15:0
MD2:1 MD0
+5V
GND
5 BIT OVERLAP CODE
Figure 2. System with Non Standard Overlaps
Figure 1. Typical 1024 Point FFT System
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