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參數(shù)資料
| 型號(hào)： | PDSP16488AMAACBR |
| 廠商： | ZARLINK SEMICONDUCTOR INC |
| 元件分類： | 數(shù)字信號(hào)處理外設(shè) |
| 英文描述： | 16-BIT, DSP-CONVOLVER, CPGA84 |
| 封裝： | PGA-84 |
| 文件頁(yè)數(shù)： | 26/30頁(yè) |
| 文件大?。?/td> | 290K |
| 代理商： | PDSP16488AMAACBR |
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PDSP16488A MA
5
Figure 3. Line Delay Allocations in Single Device Interlaced Systems
*
ODD
FIELD
N+4
512
8 X 8
ARRAY
Output is shifted
by 1 line in
every field
FIELD
DELAY
VIDEO
LINE N+2
ODD
FIELD
N+1
N-1
N
N-2
Delay is By-Passed
[REG B,BIT 7 IS SET]
N+2
IP7:0
L7:0
512
8 X 8
ARRAY
Output is shifted
by 2 lines in
every field
FIELD
DELAY
VIDEO
LINE N+4
N+3
N+1
N
N-2
N-1
N-3
*
N+2
IP7:0
L7:0
1024
4 X 4
OR
8 X 4
ARRAY
FIELD
DELAY
VIDEO
LINE N+2
N+1
N - 1
Output is shifted
by 1 line in
every field
N
LINE N-2
LINE N-1
LINE N
LINE N+1
LINE N+2
5 X 5 WINDOW
C0
C1
C2
C3
C4
C32
C33
C34
C35
C36
C40
C41
C42
C43
C44
C8
C9
C10
C11
C12
C48
C49
C50
C51
C52
LINE N-3
LINE N-2
LINE N-1
LINE N
LINE N+1
LINE N+2
LINE N+3
C48
C49
C50
C51
C52
C53
C54
C40
C41
C42
C43
C44
C45
C46
C8
C9
C10
C11
C12
C13
C14
C16
C17
C18
C19
C20
C21
C22
C32
C33
C34
C35
C36
C37
C38
C0
C1
C2
C3
C4
C5
C6
C30
C29
C28
C27
C26
C25
C24
8 X 8 WINDOW
LINE N-1
LINE N
LINE N+1
3 X 3 WINDOW
C4
C5
C9
C6
C10
C2
C0
C1
C8
IP7:0
L7:0
Delay is By-Passed
[REG B,BIT 7 IS SET]
*
C31
C56
C57
C58
C59
C60
C61
C62
C63
C23
C55
C15
C47
C7
C39
LINE N+4
ODD
FIELD
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| PDSP16488AMAGCPR | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:Single Chip 2D Convolver with Integral Line Delays |
| PDSP16488B0 | 制造商:MITEL 制造商全稱:Mitel Networks Corporation 功能描述:Single Chip 2D Convolver with Integral Line Delays |
| PDSP16488B0AC | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Video Convolver |
| PDSP16488B0GC | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Video Convolver |
| PDSP16488C0 | 制造商:MITEL 制造商全稱:Mitel Networks Corporation 功能描述:Single Chip 2D Convolver with Integral Line Delays |
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