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參數(shù)資料
| 型號： | PDSP16520 |
| 廠商： | Zarlink Semiconductor Inc. |
| 英文描述： | 32K BUCKET BUFFER |
| 中文描述： | 32K的鏟斗緩沖區(qū) |
| 文件頁數(shù)： | 8/11頁 |
| 文件大?。?/td> | 302K |
| 代理商： | PDSP16520 |
PDSP16540
6
STATIC ELECTRICAL CHARACTERISTICS
Operating Conditions (unless otherwise state)
Tamb = 0 C to +70
°
C.
Vcc = 5.0v
±
10%
ABSOLUTE MAXIMUM RATINGS [See Notes]
Supply voltage Vcc
Input voltage V
Output voltage V
Clamp diode current per pin I
(see note 2)
Static discharge voltage (HMB)
Storage temperature T
Ambient temperature with power applied T
AMB
-0.5V to 7.0V
-0.5V to Vcc + 0.5V
-0.5V to Vcc + 0.5V
18mA
500V
-65
°
C to 150
°
C
0
°
C to 70
°
C
150
°
C
3000mW
Junction temperature
Package power dissipation
Thermal resistances
Junction to case
JC
5
°
C/W
NOTES ON MAXIMUM RATINGS
1. Exceeding these ratings may cause permanent damage.
Functional operation under these conditions is not implied.
2. Maximum dissipation or 1 second should not be exceeded,
only one output to be tested at any one time.
3. Exposure to absolute maximum ratings for extended
periods may affect device reliablity.
4. Current is defined as positive into the device.
Delay from output
high to output
high impedance
Test
Waveform - measurement level
Delay from output
low to output
high impedance
H
V
0.5V
V
0.5V
L
1.5V
0.5V
1.5V
0.5V
Delay from output
high impedance to
output low
Delay from output
high impedance to
output high
V - Voltage reached when output driven high
V - Voltage reached when output driven low
The amount of overlapping is dependent on the needs of
a particular application, and is usually subject to some com-
promise. If the above maximum writing rates are marginally
not adequate, the amount of overlap can possibly be reduced
to achieve the required performance. Mode control inputs
MD2:1 should then all be tied high, and outputs D9:5 used as
inputs during reset to define the number of new words to be
written.
SUPPORTING REAL ONLY TRANSFORMS
If MD5 is tied high the PDSP16540 will support the
PDSP16510 when two concurrent 1024 point real transa-
forms are to be performed. It does not suppoprt block overlap-
ping in this mode.
Real only data is written to the buffer using the IP15:0
inputs, and the IP31:16 inputs are redundant. Two blocks of
data are acquired before DAV goes active, and both blocks are
then read in parallel using all thirty two outputs.
MD0,1, and 2 must be tied low in order to define blocks of
1024 words which totally consist of new data. The RMF flag is
not needed by the PDSP16510, but will actually go active after
the defined number of words in the second block have been
loaded. Control Register Bits 8:6 in the PDSP16510 must be
set to 101 in order to expect data on both its real and imaginary
inputs.
Units
V
V
V
V
μ
A
pF
μ
A
mA
Symbol
V
OH
V
OL
V
IH
V
IL
I
IN
C
IN
I
OZ
I
SC
Min.
2.4
-
2.8
-
-10
-50
10
Value
Typ.
10
Max.
-
0.4
0.8
+10
+50
300
Conditions
I
OH
= 4mA
I
OL
= -4mA
GND < V
IN
< V
CC
GND < V
OUT
< V
CC
V
CC
= Max
Characteristic
Output high voltage
Output low voltage
Input high voltage
Input low voltage
Input leakage current
Input capacitance
Output leakage current
Output S/C current
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| PDSP16540 | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:32K BUCKET BUFFER |
| PDSP16540A0GC | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:MISC MEMORY|QFL|132PIN|PLASTIC |
| PDSP16540B0AC | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:MISC MEMORY|PGA|84PIN|PLASTIC |
| PDSP16540B0GC | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:MISC MEMORY|QFL|132PIN|PLASTIC |
| PDSP16540C0AC | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:MISC MEMORY|PGA|84PIN|PLASTIC |
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