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參數(shù)資料
| 型號： | PDU1016H |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | 4-BIT, ECL-INTERFACED PROGRAMMABLE DELAY LINE |
| 中文描述： | 4位，經(jīng)過ECL接口可編程延遲線 |
| 文件頁數(shù)： | 2/5頁 |
| 文件大小： | 48K |
| 代理商： | PDU1016H |
PDU1016H
Doc #97044
DATA DELAY DEVICES, INC.
2
11/1/01
Tel: 973-773-2299
Fax: 973-773-9672
http://www.datadelay.com
APPLICATION NOTES
ADDRESS UPDATE
The PDU1016H is a memory device. As such,
special precautions must be taken when
changing the delay address in order to prevent
spurious output signals. The timing restrictions
are shown in Figure 1.
After the last signal edge to be delayed has
appeared on the OUT pin, a minimum time, TOAX,
is required before the address lines can change.
This time is given by the following relation:
TOAX = max { (Ai - A i-1) * TINC , 0 }
where A i-1 and Ai are the old and new address
codes, respectively. Violation of this constraint
may, depending on the history of the input signal,
cause spurious signals to appear on the OUT pin.
The possibility of spurious signals persists until
the required TOAX has elapsed.
A similar situation occurs when using the ENB
signal to disable the output while IN is active. In
this case, the unit must be held in the disabled
state until the device is able to “clear” itself. This
is achieved by holding the ENB signal high and
the IN signal low for a time given by:
TDISH = Ai * TINC
Violation of this constraint may, depending on the
history of the input signal, cause spurious signals
to appear on the OUT pin. The possibility of
spurious signals persists until the required TDISH
has elapsed.
INPUT RESTRICTIONS
There are three types of restrictions on input
pulse width and period listed in the AC
Characteristics table. The recommended
conditions are those for which the delay tolerance
specifications and monotonicity are guaranteed.
The suggested conditions are those for which
signals will propagate through the unit without
significant distortion. The absolute conditions
are those for which the unit will produce some
type of output for a given input.
When operating the unit between the
recommended and absolute conditions, the
delays may deviate from their values at low
frequency. However, these deviations will remain
constant from pulse to pulse if the input pulse
width and period remain fixed. In other words,
the delay of the unit exhibits frequency and pulse
width dependence when operated beyond the
recommended conditions. Please consult the
technical staff at Data Delay Devices if your
application has specific high-frequency
requirements.
Please note that the increment tolerances listed
represent a design goal. Although most delay
increments will fall within tolerance, they are not
guaranteed throughout the address range of the
unit. Monotonicity is, however, guaranteed over
all addresses.
TDISO
TOAX
TAENS
TENIS
PWIN
TDA
PWOUT
TDISH
A3-A0
ENB
IN
OUT
Figure 1: Timing Diagram
A i-1
Ai
TAIS
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| PDU1016H-.5 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:4-BIT, ECL-INTERFACED PROGRAMMABLE DELAY LINE |
| PDU1016H-.5C4 | 制造商:DATADELAY 制造商全稱:Data Delay Devices, Inc. 功能描述:4-BIT, ECL-INTERFACED PROGRAMMABLE DELAY LINE |
| PDU1016H-.5M | 制造商:DATADELAY 制造商全稱:Data Delay Devices, Inc. 功能描述:4-BIT, ECL-INTERFACED PROGRAMMABLE DELAY LINE |
| PDU1016H-.5MC4 | 制造商:DATADELAY 制造商全稱:Data Delay Devices, Inc. 功能描述:4-BIT, ECL-INTERFACED PROGRAMMABLE DELAY LINE |
| PDU1016H0.5 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Logic IC |
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