參數(shù)資料
型號(hào): PDU10256H-1MC5
廠商: DATA DELAY DEVICES INC
元件分類: 通用總線功能
英文描述: 8-BIT, ECL-INTERFACED PROGRAMMABLE DELAY LINE (SERIES PDU10256H)
中文描述: ACTIVE DELAY LINE, TRUE OUTPUT, DSO40
封裝: SMD-40
文件頁數(shù): 5/5頁
文件大?。?/td> 45K
代理商: PDU10256H-1MC5
PDU10256H
Doc #97047
12/17/97
DATA DELAY DEVICES, INC.
3 Mt. Prospect Ave. Clifton, NJ 07013
5
DELAY LINE AUTOMATED TESTING
TEST CONDITIONS
INPUT:
Ambient Temperature:
25
o
C
±
3
o
C
Supply Voltage (Vcc):
-5.0V
±
0.1V
Input Pulse:
OUTPUT:
Load:
C
load
:
Threshold:
50
to -2V
5pf
±
10%
(V
OH
+ V
OL
) / 2
(Rising & Falling)
Standard 10KH ECL
levels
50
Max.
2.0 ns Max. (measured
between 20% and 80%)
PW
IN
= 1.5 x Total Delay
PER
IN
= 10 x Total Delay
Source Impedance:
Rise/Fall Time:
Pulse Width:
Period:
NOTE:
The above conditions are for test only and do not in any way restrict the operation of the device.
OUT
OUT
TRIG
IN
REF
TRIG
Test Setup
DEVICE UNDER
TEST (DUT)
OSCILLOSCOPE
PULSE
GENERATOR
IN
ADDRESS SELECT
Timing Diagram For Testing
T
RISE
T
FALL
PER
IN
PW
IN
T
RISE
T
FALL
20%
20%
80%
50%
50%
50%
V
IH
V
IL
V
OH
V
OL
INPUT
SIGNAL
OUTPUT
SIGNAL
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