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參數(shù)資料
| 型號(hào)： | PDU53-750 |
| 英文描述： | Programmable Delay Line |
| 中文描述： | 可編程延遲線 |
| 文件頁(yè)數(shù)： | 4/4頁(yè) |
| 文件大?。?/td> | 264K |
| 代理商： | PDU53-750 |
PDU53
DELAY LINE AUTOMATED TESTING
TEST CONDITIONS
INPUT:
Ambient Temperature:
25
o
C
±
3
o
C
Supply Voltage (Vcc):
-4.5V
±
0.1V
Input Pulse:
Source Impedance:
Rise/Fall Time:
Pulse Width:
Period:
NOTE:
The above conditions are for test only and do not in any way restrict the operation of the device.
OUTPUT:
Load:
C
load
:
Threshold:
(V
OH
+ V
OL
) / 2
(Rising & Falling)
50
to -2V
5pf
±
10%
Standard 100K ECL
levels
50
Max.
1.0 ns Max. (measured
between 20% and 80%)
PW
IN
= 10ns
PER
IN
= 100ns
OUT
OUT
TRIG
IN
REF
TRIG
Test Setup
DEVICE UNDER
TEST (DUT)
OSCILLOSCOPE
PULSE
GENERATOR
IN
ADDRESS SELECT
Timing Diagram For Testing
T
RISE
T
FALL
PER
IN
PW
IN
T
RISE
T
FALL
20%
20%
80%
50%
50%
50%
V
IH
V
IL
V
OH
V
OL
INPUT
SIGNAL
OUTPUT
SIGNAL
Doc #98003
3/18/98
DATA DELAY DEVICES, INC.
4
Tel: 973-773-2299 Fax: 973-773-9672 http://www.datadelay.com
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| PDU53-750C3 | Delay Line |
| PDU53-750M | Delay Line |
| PDU53-750MC3 | Delay Line |
| PDU53SERIES | 3-BIT. ECL-INTERFACED PROGRAMMABLE DELAY LINE |
| PDU53-1500 | Programmable Delay Line |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| PDU53-750C3 | 制造商:DATADELAY 制造商全稱:Data Delay Devices, Inc. 功能描述:3-BIT, ECL-INTERFACED PROGRAMMABLE DELAY LINE (SERIES PDU53) |
| PDU53-750M | 制造商:DATADELAY 制造商全稱:Data Delay Devices, Inc. 功能描述:3-BIT, ECL-INTERFACED PROGRAMMABLE DELAY LINE (SERIES PDU53) |
| PDU53-750MC3 | 制造商:DATADELAY 制造商全稱:Data Delay Devices, Inc. 功能描述:3-BIT, ECL-INTERFACED PROGRAMMABLE DELAY LINE (SERIES PDU53) |
| PDU53SERIES | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:3-BIT. ECL-INTERFACED PROGRAMMABLE DELAY LINE |
| PDU54 | 制造商:DATADELAY 制造商全稱:Data Delay Devices, Inc. 功能描述:4-BIT, ECL-INTERFACED PROGRAMMABLE DELAY LINE (SERIES PDU54) |
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