參數(shù)資料
型號(hào)： PE-65967
廠商： Exar Corporation
英文描述： E3/DS3/STS-1 LINE INTERFACE UNIT
中文描述： E3/DS3/STS-1線路接口單元
文件頁數(shù)： 42/55頁
文件大?。?/td> 608K
代理商： PE-65967
XRT7300
E3/DS3/STS-1 LINE INTERFACE UNIT
REV. 1.1.1
á
38
The Digital Local Loop-Back Mode, along with the Tx-
OFF feature, is useful in Redundancy System De-
sign. These two features permit the system to exe-
cute some diagnostic tests in the Back-up Line Card
without transmitting data onto the line and interfering
with the DS3/E3/STS-1 traffic from the Primary Line
Card.
The XRT7300 can be configured to operate in the
Digital Local Loop-Back Mode by employing either
one of the following two-steps.
A. If the XRT7300 is operating in the HOST Mode
Access the Microprocessor Serial Interface and write
a “1” into both the LLB and RLB bit-fields in Com-
mand Register 4.
B. If the XRT7300 is operating in the Hardware
Mode
Set both the LLB input pin (pin 14) and the RLB input
pin (pin 15) to “High”.
N
OTES
:
1. The Digital Local Loop-Back Mode feature works
even if the transmitter is turned off via the TXOFF
feature.
2. The XRT7300 automatically declares an LOS Con-
dition any time it has been configured to operate in
either the Analog Local Loop-Back or Digital Local
Loop-Back Modes. Consequently, the MUTing -
upon -LOS must be disabled prior to configuring
the device to operate in either of these local Loop-
Back modes.
T
HE
R
EMOTE
L
OOP
-B
ACK
M
ODE
When the XRT7300 is configured to operate in the
Remote Loop-Back Mode, it ignores any signals that
are input to the TPDATA and TNDATA input pins. The
XRT7300 receives the incoming line signal via the
RTIP and RRING input pins. This data is processed
through the Receive Section of the XRT7300 and out-
puts to the Receive Terminal Equipment via the
RPOS, RNEG, RCLK1 and RCLK2 output pins. Addi-
tionally, this data is internally looped back into the
Pulse-Shaping block in the Transmit Section. At this
point, this data is routed through the remainder of the
Transmit Section of the XRT7300 and transmitted out
onto the line via the TTIP and TRING output pins.
4.3
F
IGURE
29. T
HE
D
IGITAL
L
OCAL
L
OOP
-B
ACK
PATH
IN
THE
XRT7300
AGC/
Equalizer
Peak
Detector
LOS Detector
Slicer
Clock
Recovery
Data
Recovery
Invert
Loop MUX
HDB3/
B3ZS
Decoder
LOSTHR
SDI
SDO/LCV
SCLK
CS
REGRESET
RTIP
RRING
REQDIS
RCLK1
RCLK2
RPOS
RNEG
DECODIS
RLOS
LLB
RLB
ENCODIS
TAOS
TPDATA
TNDATA
TCLK
RLOL EXCLK
Device
Monitor
MTIP
MRING
Transmit
Logic
Duty Cycle Adjust
TXLEV
TXOFF
DMO
TTIP
TRING
Pulse
Shaping
HDB3/
B3ZS
Encoder
Serial
Processor
Interface
Digital Local
Loop-Back Path
COMMAND REGISTER CR4 (ADDRESS = 0X04)
D4
D3
D2
D1
D0
X
STS-1/DS3
E3
LLB
RLB
X
X
X
1
1
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