參數(shù)資料
型號： PE12316
廠商： Electronic Theatre Controls, Inc.
英文描述： Triple Incremental Encoder
中文描述： 三增量編碼器
文件頁數(shù)： 11/29頁
文件大?。?/td> 1542K
代理商： PE12316
PE12316
Triple
Incremental Encoder
February 6, 2003 Preliminary (Version 1.1)
Reset Operation:
A total reset is initiated by pulling the /RESET
pin low. This will clear the counters to zero,
reset the D flip-flops at the inputs of the
quadrature signals (Ua1n and Ua2n), clear the
latches that inhibit the load register pulse, and
load zero into the output register.
February 6, 2003 (Preliminary Version 1.1)
Page 11/29
PE12316
To avoid a spurious count error (+/- 1) after a
reset, the Ua1n and Ua2n inputs should be held
to the values indicated in
Table 4
during and just after the reset pulse.
MODE
0
1-5
6-7
Ua1n
X
H
L
Ua2n
X
H
L
Table 4 Mode Selection
Cascading Devices
The /KLI-KLOn pins of all cascaded PE12316’s
should be tied together, so that all of the devices
load their output registers at the same time.
When the ‘Master’ generates a pulse for the
other PE12316s, /KLI-KLOn on the ‘Master’
works as an output, and /KLI-KLOn on the
Write Operation
A number may be preloaded into the counter by
pulling /CS and /WE low while using /A0 and /A3
to direct the value on the data bus to the
selected byte of the counter and /A1 & /A2 to
select the required
Read Operation
When in Modes 0 to 5 the contents of the
counter can be read at any time by pulling /CS
and /RD low. The channel is selected by using
/A1 & /A2. Within this channel the most
significant byte may be selected by setting /A3 to
low, and the least significant byte may be read
by setting /A0 and /A3 high. This will cause a
load output register pulse to be generated and
/KLI-KLOn will go low during the next low clock
pulse. /READY will also go low as the clock goes
low, and will stay low until /CS and/or /RD go
high.
‘Slaves’ work as inputs. The /CARRY output of
one device should be tied to the /UP input of the
next device in the cascade. Similarly, /BORROW
should be connected to /DOWN. For details see
Figure 14
.
channel. This will cause /READY to go low on the
next falling clock edge, and remain low until /CS
and /WE go high. See
Figure 12
.
The load output register pulse stores the current
value of the counter in a 16-bit latch register and
/A0 /A3 direct the selected byte through a
multiplexer to the outputs : /CS and /RD also
enable the 3-stat outputs – see
Figure 11
. The
output register will be loaded immediately if /KLI-
KLOn is pulled low externally, this signal normally
comes from a cascaded device.
For Modes 6 & 7 see the earlier description.
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